CN101341583B - Ⅲ-ⅴ族半导体器件的电介质界面 - Google Patents

Ⅲ-ⅴ族半导体器件的电介质界面 Download PDF

Info

Publication number
CN101341583B
CN101341583B CN2006800444311A CN200680044431A CN101341583B CN 101341583 B CN101341583 B CN 101341583B CN 2006800444311 A CN2006800444311 A CN 2006800444311A CN 200680044431 A CN200680044431 A CN 200680044431A CN 101341583 B CN101341583 B CN 101341583B
Authority
CN
China
Prior art keywords
zone
chalkogenide
dielectric
reg
alinsb
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2006800444311A
Other languages
English (en)
Other versions
CN101341583A (zh
Inventor
J·K·布拉斯克
S·达塔
M·L·多奇
J·M·布莱克威尔
M·V·梅茨
J·T·卡瓦利罗斯
R·S·乔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN101341583A publication Critical patent/CN101341583A/zh
Application granted granted Critical
Publication of CN101341583B publication Critical patent/CN101341583B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3141—Deposition using atomic layer deposition techniques [ALD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H01L29/7784—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material with delta or planar doped donor layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31616—Deposition of Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31645—Deposition of Hafnium oxides, e.g. HfO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Abstract

本发明描述了III-V族半导体器件及制造方法。通过硫族化物区域将高k电介质与限制区域对接。

Description

Ⅲ-Ⅴ族半导体器件的电介质界面
技术领域
本发明涉及III-V族半导体器件领域。背景技术
当今的大多数集成电路都基于硅、元素周期表的IV族元素。已知III-V族元素的化合物、如砷化镓(GaAs)、锑化铟(InSb)和磷化铟(InP)具有远优于硅的半导体属性，包括更高的电子迁移率以及饱和速度。不像III-V族化合物，硅容易氧化形成几乎完美的电气界面。这种天赋才能使得用二氧化硅的几个原子层就能几乎完全限制电荷。相比之下，III-V族化合物的氧化物的质量较差，例如，它们含有缺陷、陷阱电荷，并且在化学上复杂。
已经基于肖特基金属栅和InSb阱提出了量子阱场效应晶体管(QWFET)。它们在降低有效功率耗散方面比基于硅的技术更有前途，并呈现出改进的高频性能。可惜，由于来自例如InSb/AlInSb表面上的栅极金属的费米能级钉扎的低肖特基势垒，断开状态的栅极泄漏电流很高。
已经提出将高k栅极绝缘体用于QWFET。例如，参见2005年1月3日提交的标题为“QUANTUM WELL TRANSISTOR USINGHIGH DIELECTRIC CONSTANT DIELECTRIC LAYER”的No.11/0208378。然而，在高k材料与例如InSb/AlInSb表面之间的对接方面存在问题。附图说明
图1示出硅衬底与金属栅之间的现有技术高k电介质界面。
图2示出III-V族限制区域与金属栅之间的界面，包括如下所述的高k电介质和硫族化物区域。
图3示出通过硫族化物区域与高k电介质对接的限制区域。
图4A示出二苯基二硫化合物，其中苯基被替代了。
图4B示出在限制区域与高k电介质之间位置的图4A的化合物。
图5示出用于在III-V族半导体器件中形成金属栅所执行的过程。
图6是示出与肖特基金属栅相比在栅极泄漏上使用高k电介质的好处的图表。
图7是具有氧化铝(Al2O3)高k电介质层的半导体器件的截面正视图。
图8是具有高k电介质和凹入金属栅的III-V族半导体器件的截面正视图。具体实施方式
关于在半导体器件中将高k电介质与III-V族限制区域对接方面来描述过程和器件。在以下描述中，描述了大量具体化学性质以及其它细节，以便提供对本发明的透彻了解。本领域的技术人员要明白，没有这些具体细节也可实施本发明。在其它情况下，没有详细描述众所周知的处理步骤，以免不必要地影响对本发明的理解。
图1示出金属栅13与单晶硅体或衬底10之间的界面。最典型的是，硅10包括具有栅极13的场效应晶体管的沟道区域，用于控制晶体管。当沟道区域与栅极之间的绝缘层的等效氧化层厚度(EOT)在
Figure S2006800444311D00021
范围、并且优选地在
Figure S2006800444311D00022
范围时，这类器件的性能特别好。虽然二氧化硅(SiO2)提供了极好的电介质，但是用如此薄的层，难以获得可靠的二氧化硅电介质。相反，使用高k材料(例如介电常数为10或更大)。如图1所示，首先在硅10上形成二氧化硅区域11(或者是天然的)。然后在二氧化硅区域11上形成高k电介质12、如二氧化铪(HfO2)。接下来在高k电介质上形成通常具有目标功函数的金属栅。高k电介质、如HfO2或二氧化锆(ZrO2)提供极好的界面。可利用诸如在原子层淀积(ALD)过程中用于HfO2淀积的醇盐前体等有机前体，在低温淀积过程中形成高k电介质。用电子束蒸发或溅射形成的金属栅可以是铂、钨、钯、钼或其它金属。
如图1结构的右侧所示，EOT包括与硅10的上表面关联的大约
Figure S2006800444311D00031
由单晶结构表面附近的缺陷引起。在此之上，示出了大约
Figure S2006800444311D00032
的二氧化硅区域11。然后，在ALD过程中形成高k电介质，它的EOT为
Figure S2006800444311D00033
图1所示结构的合成EOT为
Figure S2006800444311D00034
图1结构的左侧，示出了区域的物理厚度(PT)。可以看到，与SiO2区域11相比，高k电介质比较厚(大约
Figure S2006800444311D00035
)。这个比较厚的区域允许形成具有低EOT
Figure S2006800444311D00036
的可靠高质量电介质。
如前面所述，在使用III-V族化合物的情况下，难以产生图1结构的对应界面。由这些化合物形成的氧化物质量较差，并且不能很好地粘附于高k电介质。
在图2中，示出了III-V族化合物与高k电介质之间的界面，下面更全面地进行描述。作为硫族化物界面区域的一个实施例，III-V族区域20示为具有界面区域21的桥接硫(S)原子。如将要描述的，这些桥接原子允许更好地匹配高k电介质区域22，对于一个实施例示为HfO2。
图3结构的EOT包括与III-V族化合物的上表面关联的大约
Figure S2006800444311D00037
如限制区域20，具体来说，包括这个区域上没有完全去除的天然氧化物以及限制区域中的晶格缺陷。界面21可以是硫族化物，诸如氧(O)、S、硒(Se)、碲(Te)。(较重的硫族化物钋(Po)由于其放射性而不可取。)对于所示实施例，界面区域21的EOT大约为
Figure S2006800444311D00038
对应于几个原子层。这个区域的PT为
Figure S2006800444311D00041
在此之上，形成PT大约为
Figure S2006800444311D00042
且EOT为
Figure S2006800444311D00043
的高k电介质区域22。最后，使用与图1的金属栅13相似的金属栅23。
在典型晶体管中，将例如InSb的量子阱限制在变质缓冲区或限制层(例如AlInSb)之间。这些层具有比阱更高的带隙，以便减轻量子阱的窄带隙对器件泄漏和击穿的影响。
在图3中，硫族化物界面区域又示为在电介质区域30与III-V族限制区域32之间。硫族化物由“X”表示，其中原子层数示为“n”。对于氧，n通常大于1，例如为3。可使用空间氧化剂(okioxidizingagent)(例如二叔丁基过氧化物或者二异丙基过氧化物)来传递具有大块离去基团的含氧取代基(例如O-t Bu)，它还可取地与标准ALD前体反应。这防止进一步与大气反应。S或Se优选地等于1、2或3。可由一价二聚物来淀积此膜。可使用多个二有机二硫族化物类中的任一个。
在图5中，示出一个过程，开始于生长III-V族量子阱50，通常在第一限制层上进行。又如上所述，III-V族阱可包括InSb或InP。如上所述，在另一个过程51中，在量子阱上形成限制区域或层。这对应于例如图2的区域20。限制层通常是与阱相容的材料，但具有更大的带隙。对于InSb阱，可使用类金属AlInSb。举例来说，可使用分子束外延或金属有机化学汽相淀积来执行过程50和51。
在形成硫族化物层之前，去除限制层上的天然氧化物和任何其它氧化物。可通过用例如柠檬酸、HCl或HF等酸对表面进行处理，来执行图5的过程52。
随后，如过程53所示，形成硫族化物层。对于一个实施例，结合图4A和图4B示出这种形成。在图4A中，示出二苯基二硫化合物，它最终留下了并置在含类金属III-V族限制区域与高k电介质之间的硫族化物膜。可使用其它二硫族化物，例如二硒化物。此外，可使用其它前体，例如苯环等。在二苯基的情况下，一个苯基示为由限制层的锑原子取代，而另一个用例如来自用于形成高k电介质的前体之一的Hf或Al原子取代。如图4B所示，这留下了S桥接原子，其中二硫族化物包括S。因此，二苯基原子在图5的过程53期间、而另一个在过程54期间由高k电介质的前体取代。可用另一个二硫族化物来获得同样的结果。可使用用于形成HfO2或ZrO2的普通前体。
在一个实施例中，封闭层是AlInSb，如上所述。在使用这个的情况下，可将Al2O3用作高k电介质，以便使化合价失配最小化。可采用ALD过程、使用三甲基铝(TMA)和水前体来淀积Al2O3。
最后，如图5所示，进行金属栅淀积55。此外，可使用普通处理来形成栅极。由于III-V族材料可具有低熔点、例如对于InSb为525℃，所以在一个实施例中将ALD用于栅极淀积。在将Al2O3用作高k电介质的情况下，可使用铝栅来提供更大相容性。
图6示出与肖特基金属栅相对比通过使用高k电介质、如Al2O3和金属栅得到的栅极泄漏减小。在图6中可容易看出，采用高k电介质，泄漏差要小几个数量级。图6的结果是针对铝栅、Al2O3电介质、AlInSb限制层和InSb量子阱。
图7示出可采用上述处理来制造的晶体管的结构。这个实施例特别适合于像耗尽型的器件，因为例如在没有将栅极嵌入限制层时，它适合于图8的器件。在一个实施例中，较低封闭区域包括例如在半绝缘GaAs衬底上形成的Al.15In.85Sb层70。然后，在较低限制层上生长例如InSb的量子阱72。随后，形成上限制层73，在一个实施例中其包括Al.20In.80Sb。这层包括供体区域，更具体来说，在一个实施例中为Te掺杂区域。Te掺杂为量子阱73提供载流子。可使用分子束外延或金属有机化学汽相淀积来生长图7的多层结构。通过允许Te(或Si)掺杂剂例如从固体源流入分子束外延室来形成掺杂供体区域。
层73的厚度连同栅极78的功函数共同确定晶体管的阈值电压，并且如前面所述，为图7的实施例提供像耗尽型的器件。因此，为栅极选择较低功函数，以便降低阈值电压。在图7中还示出了源极触点76和漏极触点77以及铝栅78。举例来说，在一个实施例中，层70可以为3μm厚，量子阱72可以为20nm厚，限制层73可以为5nm厚，并且可将Teδ掺杂供体区域掺杂到1-1.8×1012cm-2级别，μ等于18-25000cm-2v-1s-1，其中栅极长度为85nm。
图8示出另一个实施例，其中凹入的栅极用于增大电压阈值，以便提供像更增强型的器件。此外，存在较高带隙、较低限制层80、量子阱81以及通过蚀刻剂阻止层90分隔开的两个掺杂上限制层91和92。分别如δ掺杂平面82和89所示掺杂两个层91和92。将高k电介质87凹入层92中，如金属栅88那样。正是这种凹入和栅极88的功函数金属选择提供了增大的阈值电压。层厚度、掺杂级等可与图7的实施例相同。附加层92的厚度可为45nm。
这样，在几个实施例中描述了III-V族限制区域与高k电介质区域之间的界面以及使用该界面的器件。附录AWilliam E.Alford，Reg.No.37,764；Farzad E.Amini，Reg.No.42,261；Vincent H.Anderson，Reg.No.54,962；Anthony H.Azure，Reg.No.52,580；W.Thomas Babbitt，Reg.No.39,591；Jordan M.Becker，Reg.No.39,602；Todd M.Becker，Reg.No.43,487；Michael A.Bernadicou，Reg.No.35,934；Roger W.Blakely，Jr.，Reg.No.25,831；R.AlanBurnett，Reg.No.46,149；Gregory D.Caldwell，Reg.No.39,926；Cory G.Claassen，Reg.No.50,296；Thomas M.Coester，Reg.No.39,637；Mimi D.Dao，Reg.No.45,628；Stephen M.De Klerk，Reg.No.46,503；Daniel M.De Vos，Reg.No.37,813；Elena B.Dreszer，Reg.No.55,128；Nathan P.Elder，Reg.No.55,150；Thomas S.Ferrill，Reg.No.42,532；Adam Furst，Reg.No.51,710；Angelo J.Gaz，Reg.No.45,907；James Y.Go，Reg.No.40，621；James A.Henry，Reg.No.41,064；Willmore F.Holbrow III，Reg.No.41,845；Sheryl Sue Holloway，Reg.No.37,850；George W Hoover II，Reg.No.32,992；Eric S.Hyman，Reg.No.30,139；Aslam A.Jaffery，Reg.No.51,841；Eric T.King，Reg.No.44,188；Steven Laut，Reg.No.47,736；Gordon R.Lindeen III，Reg.No.33,192；JanCarol Little-Washington，Reg.No.41,181；Joseph Lutz，Reg.No.43,765；Michael J.Maille，Reg.No.36,591；Paul A.Mendonsa，Reg.No.42,879；Jonathan S，Miller，Reg.No.48,534；Heather M.Molleur，Reg.No.50,432；Thinh V.Nguyen，Reg.No.42,034；Robert B.O′Rourke，Reg.No.46,972；Daniel E.Ovanezlan，Reg.No.41,236；Marina G.Portnova，Reg.No.45,750；Jon C.Reali，Reg.No.54,391；William W.Schaal，Reg.No.39,018；James C.Scheller，Reg.No.31,195；Kevin G.Shao，Reg.No.45,095；StanleyW.Sokoloff，Reg.No.25,128；Judith A.Szepesi，Reg.No.39,393；Edwin H.Taylor，Reg.No.25,129；Lisa Tom，Reg.No.52,291；Mark C.Van Ness，Reg.No.39,865；Thomas A.Van Zandt，Reg.No.43,219；Lester J.Vincent，Reg.No.31,460；Mark L.Watson，Reg.No.46,322；Thomas C.Webster，Reg.No.46,154；Chui-Kiu Teresa Wong，Reg.No.48,042；and Norman Zafman，Reg.No.26,250；my patent attorneys，and Chze KoonChua，Reg.No.53,831；Eric Replogle，Reg.No.52,161 and Brent Vecchla，Reg.No.48,011；my patent agents；of BLAKELY，SOKOLOFF，TAYLOR & ZAFMAN LLP，withoffices located at 12400 Wilshire Boulevard，7th Floor，Los Angeles，California 90025，telephone(310)207-3800；and Alan K.Aldous，Reg.No.31,905；Rob D.Anderson，Reg.No.33,826，Shireen I.Bacon，Reg.No.40,494；Michael R.Barre，Reg.No.44,023；R.Edward Brake.Reg.No.37,784；Glen B.Choi，Reg.No.43,546；Ted A.Crawford，Reg.No.50,610；Robert Diehl，Reg.No.40,992；Jeffrey S.Draeger，Reg.No.41,000；CynthiaThomas Faatz，Reg.No.39,973；James S.Finn，Reg.No.38,450，Christopher Gagne，Reg.No.36,142；Sharmini N.Green，Reg.No.41,410；Robert Greenberg，Reg.No.44,133；Bradley Greenwald，Reg.No.34,341；Robert D.Hinchliffe，Reg.No.55,268，JuliaA.Hodge，Reg.No.46,775，Libby H.Hope，Reg.No.46,774，Jeffrey B.Huter，Reg.No.41,086；B.Delano Jordan，Reg.No.43,698，Issac Lin，Reg.No.50,672；AnthonyMartinez，Reg.No.44,223；Molly A.McCall，Reg.No.46,126，Erik M.Metzger，Reg No.53,320，Michael J.Nesheiwat，Reg.No.47,819；Dennis A.Nicholls，Reg.No.42,036；Alan Pedersen-Giles，Reg No.39,996，Cathy L.Peterson，Reg.No.41,249，Philip A.Pedigo，Reg.No.52,107；Michael D.Plimler，Reg.No.43,004；Michael Proksch，Reg.No.43,021；Kevin A.Reif，Reg.No.36,381；Crystal D.Sayles，Reg.No.44,318；JustinScout，Reg.No.54,431，Kenneth M.Seddon，Reg.No.43,105；Mark Seeley，Reg.No.32,299；Ami P.Shah，Reg.No.42,143；David Simon，Reg.No.32,756；Steven P.Skabrat，Reg.No.36,279；Paul E.Steiner，Reg.No.41,326；Jonl D.Stutman-Horn，Reg.No.42,173；David Tran，Reg.No.50,804；John F.Travis，Reg.No.43,203；Kerry D.Tweet，Reg.No.45,959；Robert G.Winkle，Reg.No.37,474；Rita M.Wisor.Reg.No.41,382，Sharon Wong，Reg.No.37,760；and Steven D.Yates.Reg.No.42,242；mypatent attorneys；and George Chen，Reg.No.50,807；Sanjay S.Gadkari.Reg.No.55,796；Robert D.Hinchliffe，Reg.No.55,268；Larry Mennemeier，Reg.No.51,003；KathyJ.Ortiz，Reg.No.54,351；and Lanny Parker，Reg.No.44,281；my patent agents；ofINTEL CORPORATION；and James R.Thein，Reg.No.31,710，my patent attorney；withfull power of substitution and revocation to prosecuce this application and to transact allbusiness In the Patent and Trademark Office connected herewith.

Claims (21)

1.一种用于制造半导体器件的方法，包括：
生长III-V族化合物的第一区域；
在所述第一区域上生长AlInSb限制区域；
在所述AlInSb限制区域上形成硫族化物区域；
在所述硫族化物区域上形成电介质区域，其中所述硫族化物区域包括在所述限制区域和所述电介质区域之间的其中n大于1的[O]n桥、二硫桥或者二硒桥；以及
在所述电介质区域上形成金属栅。
2.如权利要求1所述的方法，包括：在形成所述硫族化物区域之前，从所述限制区域去除天然氧化物。
3.如权利要求1所述的方法，其中所述第一区域包括InSb或InP。
4.如权利要求3所述的方法，其中所述电介质区域包括高k电介质。
5.如权利要求4所述的方法，其中所述高k电介质包括HfO2。
6.如权利要求1所述的方法，其中所述电介质区域包括高k电介质。
7.如权利要求6所述的方法，其中所述高k电介质包括HfO2。
8.一种用于制造半导体器件的方法，包括：
形成InSb阱；
在所述InSb阱上形成AlInSb限制区域；
从所述AIInSb限制区域的表面去除天然氧化物；
在所述AlInSb限制区域的表面上形成硫族化物区域；以及
在所述硫族化物区域上形成Al2O3层，其中所述硫族化物区域包括在所述限制区域和所述Al2O3层之间的其中n大于1的[O]n桥、二硫桥或者二硒桥。
9.如权利要求8所述的方法，其中形成所述Al2O3包括：使用三甲基铝和水前体的原子层淀积(ALD)过程。
10.如权利要求8所述的方法，其中去除所述天然氧化物包括：用酸处理所述AlInSb限制区域的表面。
11.如权利要求8所述的方法，其中形成所述AlInSb限制区域包括：形成Si或Te的供体区域。
12.一种半导体器件，包括：
InSb区域；
AlInSb区域，设置在所述InSb区域上；
硫族化物区域，设置在所述AlInSb区域上；
Al2O3区域，设置在所述硫族化物区域上，其中所述硫族化物区域包括在所述AlInSb区域和所述Al2O3区域之间的其中n大于1的[O]n桥、二硫桥或者二硒桥；以及
Al栅极，设置在所述Al2O3区域上。
13.如权利要求12所述的器件，其中所述InSb区域是由AlInSb区域所限制的量子阱。
14.如权利要求13所述的器件，其中所述Al2O3是厚度小于
Figure FSB00000559492200021
的层。
15.如权利要求13所述的器件，其中所述AlInSb区域包括用Si或Te掺杂的区域。
16.如权利要求15所述的器件，包括：源极和漏极触点，设置在所述Al栅极的对侧上。
17.如权利要求16所述的器件，其中所述Al栅极凹入所述AlInSb区域，以便提供增强型晶体管。
18.一种半导体器件，包括：
III-V族元素化合物，在第一区域中；
AlInSb限制区域，具有比所述第一区域宽的带隙，设置在所述第一区域上；
硫族化物区域，设置在所述AlInSb限制区域上；
高k电介质，设置在所述硫族化物区域上，其中所述硫族化物区域包括在所述限制区域和所述高k电介质之间的其中n大于1的[O]n桥、二硫桥或者二硒桥；以及
金属栅，设置在所述高k 电介质上。
19.如权利要求18所述的半导体器件，其中所述硫族化物区域包括氧。
20.如权利要求18所述的半导体器件，其中所述硫族化物区域包括硫。
21.如权利要求18所述的半导体器件，其中所述硫族化物区域包括硒。
CN2006800444311A 2005-11-30 2006-11-17 Ⅲ-ⅴ族半导体器件的电介质界面 Expired - Fee Related CN101341583B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/292,399 2005-11-30
US11/292,399 US7485503B2 (en) 2005-11-30 2005-11-30 Dielectric interface for group III-V semiconductor device
PCT/US2006/044601 WO2007064492A1 (en) 2005-11-30 2006-11-17 Dielectric interface for group iii-v semiconductor device

Publications (2)

Publication Number Publication Date
CN101341583A CN101341583A (zh) 2009-01-07
CN101341583B true CN101341583B (zh) 2011-12-14

Family

ID=37781654

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2006800444311A Expired - Fee Related CN101341583B (zh) 2005-11-30 2006-11-17 Ⅲ-ⅴ族半导体器件的电介质界面

Country Status (6)

Country Link
US (2) US7485503B2 (zh)
EP (2) EP1955366B1 (zh)
CN (1) CN101341583B (zh)
AT (1) ATE521983T1 (zh)
TW (1) TWI335625B (zh)
WO (1) WO2007064492A1 (zh)

Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070090416A1 (en) 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US8183556B2 (en) 2005-12-15 2012-05-22 Intel Corporation Extreme high mobility CMOS logic
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
US7851780B2 (en) * 2006-08-02 2010-12-14 Intel Corporation Semiconductor buffer architecture for III-V devices on silicon substrates
US7863710B2 (en) * 2008-02-15 2011-01-04 Intel Corporation Dislocation removal from a group III-V film grown on a semiconductor substrate
US8278687B2 (en) * 2008-03-28 2012-10-02 Intel Corporation Semiconductor heterostructures to reduce short channel effects
US8129749B2 (en) * 2008-03-28 2012-03-06 Intel Corporation Double quantum well structures for transistors
US8659852B2 (en) 2008-04-21 2014-02-25 Seagate Technology Llc Write-once magentic junction memory array
US7855911B2 (en) * 2008-05-23 2010-12-21 Seagate Technology Llc Reconfigurable magnetic logic device using spin torque
US7852663B2 (en) * 2008-05-23 2010-12-14 Seagate Technology Llc Nonvolatile programmable logic gates and adders
US8309987B2 (en) 2008-07-15 2012-11-13 Imec Enhancement mode semiconductor device
US7881098B2 (en) * 2008-08-26 2011-02-01 Seagate Technology Llc Memory with separate read and write paths
US9711373B2 (en) * 2008-09-22 2017-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a gate dielectric for high-k metal gate devices
US7985994B2 (en) 2008-09-29 2011-07-26 Seagate Technology Llc Flux-closed STRAM with electronically reflective insulative spacer
US8169810B2 (en) 2008-10-08 2012-05-01 Seagate Technology Llc Magnetic memory with asymmetric energy barrier
US8039913B2 (en) * 2008-10-09 2011-10-18 Seagate Technology Llc Magnetic stack with laminated layer
US8089132B2 (en) * 2008-10-09 2012-01-03 Seagate Technology Llc Magnetic memory with phonon glass electron crystal material
US20100102405A1 (en) * 2008-10-27 2010-04-29 Seagate Technology Llc St-ram employing a spin filter
US7852667B2 (en) * 2008-10-27 2010-12-14 Seagate Technology Llc ST-RAM employing a magnetic resonant tunneling diode as a spacer layer
US8045366B2 (en) * 2008-11-05 2011-10-25 Seagate Technology Llc STRAM with composite free magnetic element
US8043732B2 (en) 2008-11-11 2011-10-25 Seagate Technology Llc Memory cell with radial barrier
US7826181B2 (en) * 2008-11-12 2010-11-02 Seagate Technology Llc Magnetic memory with porous non-conductive current confinement layer
US8289756B2 (en) 2008-11-25 2012-10-16 Seagate Technology Llc Non volatile memory including stabilizing structures
US20100148153A1 (en) * 2008-12-16 2010-06-17 Hudait Mantu K Group III-V devices with delta-doped layer under channel region
US7826259B2 (en) 2009-01-29 2010-11-02 Seagate Technology Llc Staggered STRAM cell
CN101853882B (zh) 2009-04-01 2016-03-23 台湾积体电路制造股份有限公司 具有改进的开关电流比的高迁移率多面栅晶体管
US8816391B2 (en) * 2009-04-01 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain engineering of devices with high-mobility channels
US8455860B2 (en) 2009-04-30 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing source/drain resistance of III-V based transistors
US9768305B2 (en) 2009-05-29 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Gradient ternary or quaternary multiple-gate transistor
US8617976B2 (en) 2009-06-01 2013-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain re-growth for manufacturing III-V based transistors
US7999338B2 (en) 2009-07-13 2011-08-16 Seagate Technology Llc Magnetic stack having reference layers with orthogonal magnetization orientation directions
EP2306497B1 (en) * 2009-10-02 2012-06-06 Imec Method for manufacturing a low defect interface between a dielectric and a III/V compound
US8258543B2 (en) 2009-12-07 2012-09-04 Intel Corporation Quantum-well-based semiconductor devices
US8440998B2 (en) 2009-12-21 2013-05-14 Intel Corporation Increasing carrier injection velocity for integrated circuit devices
US8633470B2 (en) * 2009-12-23 2014-01-21 Intel Corporation Techniques and configurations to impart strain to integrated circuit devices
US8936976B2 (en) * 2009-12-23 2015-01-20 Intel Corporation Conductivity improvements for III-V semiconductor devices
US8344418B2 (en) * 2009-12-23 2013-01-01 Intel Corporation Materials for interfacing high-K dielectric layers with III-V semiconductors
CN102136428B (zh) * 2011-01-25 2012-07-25 北京大学 一种锗基肖特基n型场效应晶体管的制备方法
WO2013095376A1 (en) 2011-12-20 2013-06-27 Intel Corporation Strained channel region transistors employing source and drain stressors and systems including the same
US9064709B2 (en) * 2012-09-28 2015-06-23 Intel Corporation High breakdown voltage III-N depletion mode MOS capacitors
US10134727B2 (en) 2012-09-28 2018-11-20 Intel Corporation High breakdown voltage III-N depletion mode MOS capacitors
EP2854158B1 (en) * 2013-09-27 2019-07-10 IMEC vzw Layer deposition on III-V semiconductors
KR20150073290A (ko) * 2013-12-20 2015-07-01 삼성전자주식회사 Ⅲ-ⅴ족 반도체 트랜지스터 및 그 제조방법
KR102200500B1 (ko) 2014-06-11 2021-01-07 삼성전자주식회사 전도성 박막 및 이를 포함한 전자 소자
US9716225B2 (en) 2014-09-03 2017-07-25 Micron Technology, Inc. Memory cells including dielectric materials, memory devices including the memory cells, and methods of forming same
KR102365687B1 (ko) 2015-04-21 2022-02-21 삼성전자주식회사 집적회로 소자 및 그 제조 방법

Family Cites Families (433)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4231149A (en) 1978-10-10 1980-11-04 Texas Instruments Incorporated Narrow band-gap semiconductor CCD imaging device and method of fabrication
GB2156149A (en) 1984-03-14 1985-10-02 Philips Electronic Associated Dielectrically-isolated integrated circuit manufacture
US4487652A (en) 1984-03-30 1984-12-11 Motorola, Inc. Slope etch of polyimide
US4872046A (en) * 1986-01-24 1989-10-03 University Of Illinois Heterojunction semiconductor device with <001> tilt
US4711701A (en) 1986-09-16 1987-12-08 Texas Instruments Incorporated Self-aligned transistor method
FR2604826B1 (fr) 1986-10-06 1989-01-20 France Etat Procede de formation d'une couche isolante comportant du sulfure, derives sulfures obtenus et appareillage pour la mise en oeuvre du procede
US5514885A (en) 1986-10-09 1996-05-07 Myrick; James J. SOI methods and apparatus
FR2605647B1 (fr) * 1986-10-27 1993-01-29 Nissim Yves Procede de depot en phase vapeur par flash thermique d'une couche isolante sur un substrat en materiau iii-v, application a la fabrication d'une structure mis
US4751201A (en) * 1987-03-04 1988-06-14 Bell Communications Research, Inc. Passivation of gallium arsenide devices with sodium sulfide
US4818715A (en) 1987-07-09 1989-04-04 Industrial Technology Research Institute Method of fabricating a LDDFET with self-aligned silicide
US4907048A (en) 1987-11-23 1990-03-06 Xerox Corporation Double implanted LDD transistor self-aligned with gate
US4905063A (en) 1988-06-21 1990-02-27 American Telephone And Telegraph Company, At&T Bell Laboratories Floating gate memories
JPH0214578A (ja) 1988-07-01 1990-01-18 Fujitsu Ltd 半導体装置
KR910010043B1 (ko) 1988-07-28 1991-12-10 한국전기통신공사 스페이서를 이용한 미세선폭 형성방법
US4871692A (en) * 1988-09-30 1989-10-03 Lee Hong H Passivation of group III-V surfaces
US4994873A (en) 1988-10-17 1991-02-19 Motorola, Inc. Local interconnect for stacked polysilicon device
US5346834A (en) 1988-11-21 1994-09-13 Hitachi, Ltd. Method for manufacturing a semiconductor device and a semiconductor memory device
US4906589A (en) 1989-02-06 1990-03-06 Industrial Technology Research Institute Inverse-T LDDFET with self-aligned silicide
JPH02302044A (ja) 1989-05-16 1990-12-14 Fujitsu Ltd 半導体装置の製造方法
WO1991006976A2 (en) 1989-11-07 1991-05-16 Department Of The Navy Process for producing an aluminum oxide layer on various substrates
US5328810A (en) 1990-05-07 1994-07-12 Micron Technology, Inc. Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process
KR930003790B1 (ko) 1990-07-02 1993-05-10 삼성전자 주식회사 반도체 장치의 캐패시터용 유전체
US5393680A (en) 1990-08-01 1995-02-28 Sumitomo Electric Industries, Ltd. MIS electrode forming process
US5278102A (en) 1990-08-18 1994-01-11 Fujitsu Limited SOI device and a fabrication process thereof
DE69009474T2 (de) 1990-09-14 1994-12-01 Ibm Methode zur Passivierung von geätzten Spiegelfacetten von Halbleiterlasern.
JP3061406B2 (ja) 1990-09-28 2000-07-10 株式会社東芝 半導体装置
JP3202223B2 (ja) 1990-11-27 2001-08-27 日本電気株式会社 トランジスタの製造方法
US5521859A (en) 1991-03-20 1996-05-28 Fujitsu Limited Semiconductor memory device having thin film transistor and method of producing the same
DE69213539T2 (de) 1991-04-26 1997-02-20 Canon Kk Halbleitervorrichtung mit verbessertem isoliertem Gate-Transistor
JPH05152293A (ja) 1991-04-30 1993-06-18 Sgs Thomson Microelectron Inc 段差付き壁相互接続体及びゲートの製造方法
US5346836A (en) 1991-06-06 1994-09-13 Micron Technology, Inc. Process for forming low resistance contacts between silicide areas and upper level polysilicon interconnects
US5292670A (en) 1991-06-10 1994-03-08 Texas Instruments Incorporated Sidewall doping technique for SOI transistors
JP3038063B2 (ja) 1991-09-25 2000-05-08 新一郎 植草 化合物半導体の表面不活性化方法
US5179037A (en) 1991-12-24 1993-01-12 Texas Instruments Incorporated Integration of lateral and vertical quantum well transistors in the same epitaxial stack
US5391506A (en) 1992-01-31 1995-02-21 Kawasaki Steel Corporation Manufacturing method for semiconductor devices with source/drain formed in substrate projection.
JPH05243572A (ja) 1992-02-27 1993-09-21 Fujitsu Ltd 半導体装置
US5405454A (en) 1992-03-19 1995-04-11 Matsushita Electric Industrial Co., Ltd. Electrically insulated silicon structure and producing method therefor
JP2572003B2 (ja) 1992-03-30 1997-01-16 三星電子株式会社 三次元マルチチャンネル構造を有する薄膜トランジスタの製造方法
JPH0793441B2 (ja) 1992-04-24 1995-10-09 ヒュンダイ エレクトロニクス インダストリーズ カンパニー リミテッド 薄膜トランジスタ及びその製造方法
JP3257077B2 (ja) 1992-10-20 2002-02-18 ソニー株式会社 Ｍｉｓ型半導体装置の製造方法
KR960002088B1 (ko) 1993-02-17 1996-02-10 삼성전자주식회사 에스오아이(SOI : silicon on insulator) 구조의 반도체 장치 제조방법
US5357119A (en) 1993-02-19 1994-10-18 Board Of Regents Of The University Of California Field effect devices having short period superlattice structures using Si and Ge
JPH06310547A (ja) 1993-02-25 1994-11-04 Mitsubishi Electric Corp 半導体装置及びその製造方法
EP0623963A1 (de) 1993-05-06 1994-11-09 Siemens Aktiengesellschaft MOSFET auf SOI-Substrat
US5739544A (en) 1993-05-26 1998-04-14 Matsushita Electric Industrial Co., Ltd. Quantization functional device utilizing a resonance tunneling effect and method for producing the same
US5475869A (en) 1993-05-28 1995-12-12 Nec Corporation Radio base station capable of distinguishing between interference due to collisions of outgoing call signals and an external interference noise
US6730549B1 (en) 1993-06-25 2004-05-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for its preparation
JP3778581B2 (ja) 1993-07-05 2006-05-24 三菱電機株式会社 半導体装置およびその製造方法
JPH0750410A (ja) 1993-08-06 1995-02-21 Hitachi Ltd 半導体結晶積層体及びその形成方法並びに半導体装置
JP3460863B2 (ja) 1993-09-17 2003-10-27 三菱電機株式会社 半導体装置の製造方法
US5883564A (en) 1994-04-18 1999-03-16 General Motors Corporation Magnetic field sensor having high mobility thin indium antimonide active layer on thin aluminum indium antimonide buffer layer
US5479033A (en) 1994-05-27 1995-12-26 Sandia Corporation Complementary junction heterostructure field-effect transistor
JP3317582B2 (ja) 1994-06-01 2002-08-26 菱電セミコンダクタシステムエンジニアリング株式会社 微細パターンの形成方法
JP3361922B2 (ja) 1994-09-13 2003-01-07 株式会社東芝 半導体装置
JP3378414B2 (ja) 1994-09-14 2003-02-17 株式会社東芝 半導体装置
JPH08153880A (ja) 1994-09-29 1996-06-11 Toshiba Corp 半導体装置及びその製造方法
US5602049A (en) 1994-10-04 1997-02-11 United Microelectronics Corporation Method of fabricating a buried structure SRAM cell
JPH08125152A (ja) 1994-10-28 1996-05-17 Canon Inc 半導体装置、それを用いた相関演算装置、ａｄ変換器、ｄａ変換器、信号処理システム
US5728594A (en) 1994-11-02 1998-03-17 Texas Instruments Incorporated Method of making a multiple transistor integrated circuit with thick copper interconnect
US5576227A (en) 1994-11-02 1996-11-19 United Microelectronics Corp. Process for fabricating a recessed gate MOS device
JP3078720B2 (ja) 1994-11-02 2000-08-21 三菱電機株式会社 半導体装置およびその製造方法
GB2295488B (en) 1994-11-24 1996-11-20 Toshiba Cambridge Res Center Semiconductor device
US5716879A (en) 1994-12-15 1998-02-10 Goldstar Electron Company, Ltd. Method of making a thin film transistor
JPH08204191A (ja) 1995-01-20 1996-08-09 Sony Corp 電界効果トランジスタ及びその製造方法
US5665203A (en) 1995-04-28 1997-09-09 International Business Machines Corporation Silicon etching method
JP3303601B2 (ja) 1995-05-19 2002-07-22 日産自動車株式会社 溝型半導体装置
KR0165398B1 (ko) 1995-05-26 1998-12-15 윤종용 버티칼 트랜지스터의 제조방법
US5658806A (en) 1995-10-26 1997-08-19 National Science Council Method for fabricating thin-film transistor with bottom-gate or dual-gate configuration
US5814895A (en) 1995-12-22 1998-09-29 Sony Corporation Static random access memory having transistor elements formed on side walls of a trench in a semiconductor substrate
KR100205442B1 (ko) 1995-12-26 1999-07-01 구본준 박막트랜지스터 및 그의 제조방법
US5595919A (en) 1996-02-20 1997-01-21 Chartered Semiconductor Manufacturing Pte Ltd. Method of making self-aligned halo process for reducing junction capacitance
JPH09293793A (ja) 1996-04-26 1997-11-11 Mitsubishi Electric Corp 薄膜トランジスタを有する半導体装置およびその製造方法
US5793088A (en) 1996-06-18 1998-08-11 Integrated Device Technology, Inc. Structure for controlling threshold voltage of MOSFET
JP3710880B2 (ja) 1996-06-28 2005-10-26 株式会社東芝 不揮発性半導体記憶装置
TW548686B (en) 1996-07-11 2003-08-21 Semiconductor Energy Lab CMOS semiconductor device and apparatus using the same
US5817560A (en) 1996-09-12 1998-10-06 Advanced Micro Devices, Inc. Ultra short trench transistors and process for making same
US6399970B2 (en) 1996-09-17 2002-06-04 Matsushita Electric Industrial Co., Ltd. FET having a Si/SiGeC heterojunction channel
US6063675A (en) 1996-10-28 2000-05-16 Texas Instruments Incorporated Method of forming a MOSFET using a disposable gate with a sidewall dielectric
US6063677A (en) 1996-10-28 2000-05-16 Texas Instruments Incorporated Method of forming a MOSFET using a disposable gate and raised source and drain
US6163053A (en) 1996-11-06 2000-12-19 Ricoh Company, Ltd. Semiconductor device having opposite-polarity region under channel
JPH10150185A (ja) 1996-11-20 1998-06-02 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5827769A (en) 1996-11-20 1998-10-27 Intel Corporation Method for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrode
US5773331A (en) 1996-12-17 1998-06-30 International Business Machines Corporation Method for making single and double gate field effect transistors with sidewall source-drain contacts
US5908313A (en) 1996-12-31 1999-06-01 Intel Corporation Method of forming a transistor
JP4086926B2 (ja) 1997-01-29 2008-05-14 富士通株式会社 半導体装置及びその製造方法
JPH118390A (ja) 1997-06-18 1999-01-12 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6251763B1 (en) 1997-06-30 2001-06-26 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing same
US6054355A (en) 1997-06-30 2000-04-25 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device which includes forming a dummy gate
JPH1140811A (ja) 1997-07-22 1999-02-12 Hitachi Ltd 半導体装置およびその製造方法
US5952701A (en) 1997-08-18 1999-09-14 National Semiconductor Corporation Design and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor value
US5776821A (en) 1997-08-22 1998-07-07 Vlsi Technology, Inc. Method for forming a reduced width gate electrode
US5981400A (en) 1997-09-18 1999-11-09 Cornell Research Foundation, Inc. Compliant universal substrate for epitaxial growth
US6066869A (en) 1997-10-06 2000-05-23 Micron Technology, Inc. Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor
US5976767A (en) 1997-10-09 1999-11-02 Micron Technology, Inc. Ammonium hydroxide etch of photoresist masked silicon
US5856225A (en) 1997-11-24 1999-01-05 Chartered Semiconductor Manufacturing Ltd Creation of a self-aligned, ion implanted channel region, after source and drain formation
US6120846A (en) 1997-12-23 2000-09-19 Advanced Technology Materials, Inc. Method for the selective deposition of bismuth based ferroelectric thin films by chemical vapor deposition
US5888309A (en) 1997-12-29 1999-03-30 Taiwan Semiconductor Manufacturing Company, Ltd. Lateral etch inhibited multiple for forming a via through a microelectronics layer susceptible to etching within a fluorine containing plasma followed by an oxygen containing plasma
US6117741A (en) 1998-01-09 2000-09-12 Texas Instruments Incorporated Method of forming a transistor having an improved sidewall gate structure
US6294416B1 (en) 1998-01-23 2001-09-25 Texas Instruments-Acer Incorporated Method of fabricating CMOS transistors with self-aligned planarization twin-well by using fewer mask counts
US6097065A (en) 1998-03-30 2000-08-01 Micron Technology, Inc. Circuits and methods for dual-gated transistors
US6307235B1 (en) 1998-03-30 2001-10-23 Micron Technology, Inc. Another technique for gated lateral bipolar transistors
US6087208A (en) 1998-03-31 2000-07-11 Advanced Micro Devices, Inc. Method for increasing gate capacitance by using both high and low dielectric gate material
US6215190B1 (en) 1998-05-12 2001-04-10 International Business Machines Corporation Borderless contact to diffusion with respect to gate conductor and methods for fabricating
US6232641B1 (en) 1998-05-29 2001-05-15 Kabushiki Kaisha Toshiba Semiconductor apparatus having elevated source and drain structure and manufacturing method therefor
US6114201A (en) 1998-06-01 2000-09-05 Texas Instruments-Acer Incorporated Method of manufacturing a multiple fin-shaped capacitor for high density DRAMs
US20010040907A1 (en) 1998-06-12 2001-11-15 Utpal Kumar Chakrabarti Optical device including carbon-doped contact layers
US6165880A (en) 1998-06-15 2000-12-26 Taiwan Semiconductor Manufacturing Company Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits
US6130123A (en) 1998-06-30 2000-10-10 Intel Corporation Method for making a complementary metal gate electrode technology
JP2000037842A (ja) 1998-07-27 2000-02-08 Dainippon Printing Co Ltd 電磁波吸収化粧材
US6117697A (en) 1998-07-27 2000-09-12 The United States Of America As Represented By The Secretary Of The Air Force Solid state magnetic field sensor method
US6696366B1 (en) 1998-08-17 2004-02-24 Lam Research Corporation Technique for etching a low capacitance dielectric layer
JP2000156502A (ja) 1998-09-21 2000-06-06 Texas Instr Inc <Ti> 集積回路及び方法
US5985726A (en) 1998-11-06 1999-11-16 Advanced Micro Devices, Inc. Damascene process for forming ultra-shallow source/drain extensions and pocket in ULSI MOSFET
US6262456B1 (en) 1998-11-06 2001-07-17 Advanced Micro Devices, Inc. Integrated circuit having transistors with different threshold voltages
US6114206A (en) 1998-11-06 2000-09-05 Advanced Micro Devices, Inc. Multiple threshold voltage transistor implemented by a damascene process
US6153485A (en) 1998-11-09 2000-11-28 Chartered Semiconductor Manufacturing Ltd. Salicide formation on narrow poly lines by pulling back of spacer
US6406795B1 (en) 1998-11-25 2002-06-18 Applied Optoelectronics, Inc. Compliant universal substrates for optoelectronic and electronic devices
US6200865B1 (en) 1998-12-04 2001-03-13 Advanced Micro Devices, Inc. Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gate
US6362111B1 (en) 1998-12-09 2002-03-26 Texas Instruments Incorporated Tunable gate linewidth reduction process
US6252262B1 (en) * 1998-12-15 2001-06-26 The United States Of America As Represented By The Secretary Of The Navy Metal passivating layer for III-V semiconductors, and improved gate contact for III-V-based metal-insulator-semiconductor (MIS) devices
TW406312B (en) 1998-12-18 2000-09-21 United Microelectronics Corp The method of etching doped poly-silicon
TW449919B (en) 1998-12-18 2001-08-11 Koninkl Philips Electronics Nv A method of manufacturing a semiconductor device
US6607948B1 (en) 1998-12-24 2003-08-19 Kabushiki Kaisha Toshiba Method of manufacturing a substrate using an SiGe layer
US6380558B1 (en) 1998-12-29 2002-04-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
US6150222A (en) 1999-01-07 2000-11-21 Advanced Micro Devices, Inc. Method of making a high performance transistor with elevated spacer formation and self-aligned channel regions
FR2788629B1 (fr) 1999-01-15 2003-06-20 Commissariat Energie Atomique Transistor mis et procede de fabrication d'un tel transistor sur un substrat semiconducteur
US6174820B1 (en) 1999-02-16 2001-01-16 Sandia Corporation Use of silicon oxynitride as a sacrificial material for microelectromechanical devices
JP2000243854A (ja) 1999-02-22 2000-09-08 Toshiba Corp 半導体装置及びその製造方法
US6093621A (en) 1999-04-05 2000-07-25 Vanguard International Semiconductor Corp. Method of forming shallow trench isolation
US7045468B2 (en) 1999-04-09 2006-05-16 Intel Corporation Isolated junction structure and method of manufacture
US6459123B1 (en) 1999-04-30 2002-10-01 Infineon Technologies Richmond, Lp Double gated transistor
EP1063697B1 (en) 1999-06-18 2003-03-12 Lucent Technologies Inc. A process for fabricating a CMOS integrated circuit having vertical transistors
JP2001015704A (ja) 1999-06-29 2001-01-19 Hitachi Ltd 半導体集積回路
US6218309B1 (en) 1999-06-30 2001-04-17 Lam Research Corporation Method of achieving top rounding and uniform etch depths while etching shallow trench isolation features
US6501131B1 (en) 1999-07-22 2002-12-31 International Business Machines Corporation Transistors having independently adjustable parameters
US6133593A (en) 1999-07-23 2000-10-17 The United States Of America As Represented By The Secretary Of The Navy Channel design to reduce impact ionization in heterostructure field-effect transistors
TW432594B (en) 1999-07-31 2001-05-01 Taiwan Semiconductor Mfg Manufacturing method for shallow trench isolation
US6320212B1 (en) 1999-09-02 2001-11-20 Hrl Laboratories, Llc. Superlattice fabrication for InAs/GaSb/AISb semiconductor structures
US6259135B1 (en) 1999-09-24 2001-07-10 International Business Machines Corporation MOS transistors structure for reducing the size of pitch limited circuits
FR2799305B1 (fr) 1999-10-05 2004-06-18 St Microelectronics Sa Procede de fabrication d'un dispositif semi-conducteur a grille enveloppante et dispositif obtenu
EP1091413A3 (en) 1999-10-06 2005-01-12 Lsi Logic Corporation Fully-depleted, fully-inverted, short-length and vertical channel, dual-gate, cmos fet
US6541829B2 (en) 1999-12-03 2003-04-01 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US6252284B1 (en) 1999-12-09 2001-06-26 International Business Machines Corporation Planarized silicon fin device
KR100311049B1 (ko) 1999-12-13 2001-10-12 윤종용 불휘발성 반도체 메모리장치 및 그의 제조방법
US6303479B1 (en) 1999-12-16 2001-10-16 Spinnaker Semiconductor, Inc. Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts
JP4923318B2 (ja) 1999-12-17 2012-04-25 ソニー株式会社 不揮発性半導体記憶装置およびその動作方法
JP4194237B2 (ja) 1999-12-28 2008-12-10 株式会社リコー 電界効果トランジスタを用いた電圧発生回路及び基準電圧源回路
US7391087B2 (en) 1999-12-30 2008-06-24 Intel Corporation MOS transistor structure and method of fabrication
JP3613113B2 (ja) 2000-01-21 2005-01-26 日本電気株式会社 半導体装置およびその製造方法
US6319807B1 (en) 2000-02-07 2001-11-20 United Microelectronics Corp. Method for forming a semiconductor device by using reverse-offset spacer process
JP3846706B2 (ja) 2000-02-23 2006-11-15 信越半導体株式会社 ウエーハ外周面取部の研磨方法及び研磨装置
US6483156B1 (en) 2000-03-16 2002-11-19 International Business Machines Corporation Double planar gated SOI MOSFET structure
FR2806832B1 (fr) 2000-03-22 2002-10-25 Commissariat Energie Atomique Transistor mos a source et drain metalliques, et procede de fabrication d'un tel transistor
JP3906005B2 (ja) 2000-03-27 2007-04-18 株式会社東芝 半導体装置の製造方法
KR100332834B1 (ko) 2000-03-29 2002-04-15 윤덕용 비등방성 식각을 이용한 서브마이크론 게이트 제조 방법
TW466606B (en) 2000-04-20 2001-12-01 United Microelectronics Corp Manufacturing method for dual metal gate electrode
GB2362506A (en) * 2000-05-19 2001-11-21 Secr Defence Field effect transistor with an InSb quantum well and minority carrier extraction
JP2001338987A (ja) 2000-05-26 2001-12-07 Nec Microsystems Ltd Ｍｏｓトランジスタのシャロートレンチ分離領域の形成方法
FR2810161B1 (fr) 2000-06-09 2005-03-11 Commissariat Energie Atomique Memoire electronique a architecture damascene et procede de realisation d'une telle memoire
US6526996B1 (en) 2000-06-12 2003-03-04 Promos Technologies, Inc. Dry clean method instead of traditional wet clean after metal etch
US6391782B1 (en) 2000-06-20 2002-05-21 Advanced Micro Devices, Inc. Process for forming multiple active lines and gate-all-around MOSFET
KR100545706B1 (ko) 2000-06-28 2006-01-24 주식회사 하이닉스반도체 반도체 소자 제조방법
WO2002003482A1 (de) 2000-07-04 2002-01-10 Infineon Technologies Ag Feldeffekttransistor
US6992319B2 (en) * 2000-07-18 2006-01-31 Epitaxial Technologies Ultra-linear multi-channel field effect transistor
US20020011612A1 (en) 2000-07-31 2002-01-31 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP2002047034A (ja) 2000-07-31 2002-02-12 Shinetsu Quartz Prod Co Ltd プラズマを利用したプロセス装置用の石英ガラス治具
US6403981B1 (en) 2000-08-07 2002-06-11 Advanced Micro Devices, Inc. Double gate transistor having a silicon/germanium channel region
KR100338778B1 (ko) 2000-08-21 2002-05-31 윤종용 선택적 실리사이드 공정을 이용한 모스 트랜지스터의제조방법
US6358800B1 (en) 2000-09-18 2002-03-19 Vanguard International Semiconductor Corporation Method of forming a MOSFET with a recessed-gate having a channel length beyond photolithography limit
US6387820B1 (en) 2000-09-19 2002-05-14 Advanced Micro Devices, Inc. BC13/AR chemistry for metal overetching on a high density plasma etcher
JP2002100762A (ja) 2000-09-22 2002-04-05 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP4044276B2 (ja) 2000-09-28 2008-02-06 株式会社東芝 半導体装置及びその製造方法
US6562665B1 (en) 2000-10-16 2003-05-13 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology
US7163864B1 (en) 2000-10-18 2007-01-16 International Business Machines Corporation Method of fabricating semiconductor side wall fin
US6645840B2 (en) 2000-10-19 2003-11-11 Texas Instruments Incorporated Multi-layered polysilicon process
US6413802B1 (en) 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6716684B1 (en) 2000-11-13 2004-04-06 Advanced Micro Devices, Inc. Method of making a self-aligned triple gate silicon-on-insulator device
US6472258B1 (en) 2000-11-13 2002-10-29 International Business Machines Corporation Double gate trench transistor
US6396108B1 (en) 2000-11-13 2002-05-28 Advanced Micro Devices, Inc. Self-aligned double gate silicon-on-insulator (SOI) device
US6479866B1 (en) 2000-11-14 2002-11-12 Advanced Micro Devices, Inc. SOI device with self-aligned selective damage implant, and method
JP2002198441A (ja) 2000-11-16 2002-07-12 Hynix Semiconductor Inc 半導体素子のデュアル金属ゲート形成方法
US6552401B1 (en) 2000-11-27 2003-04-22 Micron Technology Use of gate electrode workfunction to improve DRAM refresh
US20020100942A1 (en) 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6921947B2 (en) 2000-12-15 2005-07-26 Renesas Technology Corp. Semiconductor device having recessed isolation insulation film
US6413877B1 (en) 2000-12-22 2002-07-02 Lam Research Corporation Method of preventing damage to organo-silicate-glass materials during resist stripping
JP2002198368A (ja) 2000-12-26 2002-07-12 Nec Corp 半導体装置の製造方法
US6537901B2 (en) 2000-12-29 2003-03-25 Hynix Semiconductor Inc. Method of manufacturing a transistor in a semiconductor device
TW561530B (en) 2001-01-03 2003-11-11 Macronix Int Co Ltd Process for fabricating CMOS transistor of IC devices employing double spacers for preventing short-channel effect
US6975014B1 (en) 2001-01-09 2005-12-13 Advanced Micro Devices, Inc. Method for making an ultra thin FDSOI device with improved short-channel performance
US6359311B1 (en) 2001-01-17 2002-03-19 Taiwan Semiconductor Manufacturing Co., Ltd. Quasi-surrounding gate and a method of fabricating a silicon-on-insulator semiconductor device with the same
US6403434B1 (en) 2001-02-09 2002-06-11 Advanced Micro Devices, Inc. Process for manufacturing MOS transistors having elevated source and drain regions and a high-k gate dielectric
US6475890B1 (en) 2001-02-12 2002-11-05 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology
JP2002246310A (ja) 2001-02-14 2002-08-30 Sony Corp 半導体薄膜の形成方法及び半導体装置の製造方法、これらの方法の実施に使用する装置、並びに電気光学装置
US6475869B1 (en) 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
FR2822293B1 (fr) 2001-03-13 2007-03-23 Nat Inst Of Advanced Ind Scien Transistor a effet de champ et double grille, circuit integre comportant ce transistor, et procede de fabrication de ce dernier
TW582071B (en) 2001-03-20 2004-04-01 Macronix Int Co Ltd Method for etching metal in a semiconductor
JP3940565B2 (ja) 2001-03-29 2007-07-04 株式会社東芝 半導体装置及びその製造方法
JP2002298051A (ja) 2001-03-30 2002-10-11 Mizuho Bank Ltd ポイント交換サービス・システム
US6458662B1 (en) 2001-04-04 2002-10-01 Advanced Micro Devices, Inc. Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed
KR100414217B1 (ko) 2001-04-12 2004-01-07 삼성전자주식회사 게이트 올 어라운드형 트랜지스터를 가진 반도체 장치 및그 형성 방법
US6645861B2 (en) 2001-04-18 2003-11-11 International Business Machines Corporation Self-aligned silicide process for silicon sidewall source and drain contacts
US6787402B1 (en) 2001-04-27 2004-09-07 Advanced Micro Devices, Inc. Double-gate vertical MOSFET transistor and fabrication method
US6902947B2 (en) 2001-05-07 2005-06-07 Applied Materials, Inc. Integrated method for release and passivation of MEMS structures
SG112804A1 (en) 2001-05-10 2005-07-28 Inst Of Microelectronics Sloped trench etching process
KR100363332B1 (en) 2001-05-23 2002-12-05 Samsung Electronics Co Ltd Method for forming semiconductor device having gate all-around type transistor
US6635923B2 (en) 2001-05-24 2003-10-21 International Business Machines Corporation Damascene double-gate MOSFET with vertical channel regions
US6506692B2 (en) 2001-05-30 2003-01-14 Intel Corporation Method of making a semiconductor device using a silicon carbide hard mask
US6737333B2 (en) 2001-07-03 2004-05-18 Texas Instruments Incorporated Semiconductor device isolation structure and method of forming
JP2003017508A (ja) 2001-07-05 2003-01-17 Nec Corp 電界効果トランジスタ
US6534807B2 (en) 2001-08-13 2003-03-18 International Business Machines Corporation Local interconnect junction on insulator (JOI) structure
US6501141B1 (en) 2001-08-13 2002-12-31 Taiwan Semiconductor Manufacturing Company, Ltd Self-aligned contact with improved isolation and method for forming
US6764965B2 (en) 2001-08-17 2004-07-20 United Microelectronics Corp. Method for improving the coating capability of low-k dielectric layer
JP2003100902A (ja) 2001-09-21 2003-04-04 Mitsubishi Electric Corp 半導体装置の製造方法
US6689650B2 (en) 2001-09-27 2004-02-10 International Business Machines Corporation Fin field effect transistor with self-aligned gate
US6492212B1 (en) 2001-10-05 2002-12-10 International Business Machines Corporation Variable threshold voltage double gated transistors and method of fabrication
US20030085194A1 (en) 2001-11-07 2003-05-08 Hopkins Dean A. Method for fabricating close spaced mirror arrays
US7385262B2 (en) 2001-11-27 2008-06-10 The Board Of Trustees Of The Leland Stanford Junior University Band-structure modulation of nano-structures in an electric field
US6657259B2 (en) 2001-12-04 2003-12-02 International Business Machines Corporation Multiple-plane FinFET CMOS
US6967351B2 (en) 2001-12-04 2005-11-22 International Business Machines Corporation Finfet SRAM cell using low mobility plane for cell stability and method for forming
US6610576B2 (en) 2001-12-13 2003-08-26 International Business Machines Corporation Method for forming asymmetric dual gate transistor
US6555879B1 (en) 2002-01-11 2003-04-29 Advanced Micro Devices, Inc. SOI device with metal source/drain and method of fabrication
US6722946B2 (en) 2002-01-17 2004-04-20 Nutool, Inc. Advanced chemical mechanical polishing system with smart endpoint detection
US6583469B1 (en) 2002-01-28 2003-06-24 International Business Machines Corporation Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same
KR100442089B1 (ko) 2002-01-29 2004-07-27 삼성전자주식회사 노치된 게이트 전극을 갖는 모스 트랜지스터의 제조방법
DE10203998A1 (de) 2002-02-01 2003-08-21 Infineon Technologies Ag Verfahren zum Herstellen einer zackenförmigen Struktur, Verfahren zum Herstellen eines Transistors, Verfahren zum Herstellen eines Floating Gate-Transistors, Transistor, Floating Gate-Transistor und Speicher-Anordnung
US6784071B2 (en) 2003-01-31 2004-08-31 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement
US20030151077A1 (en) 2002-02-13 2003-08-14 Leo Mathew Method of forming a vertical double gate semiconductor device and structure thereof
JP3782021B2 (ja) 2002-02-22 2006-06-07 株式会社東芝 半導体装置、半導体装置の製造方法、半導体基板の製造方法
US6660598B2 (en) 2002-02-26 2003-12-09 International Business Machines Corporation Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region
JP4370104B2 (ja) 2002-03-05 2009-11-25 シャープ株式会社 半導体記憶装置
US6639827B2 (en) 2002-03-12 2003-10-28 Intel Corporation Low standby power using shadow storage
US6635909B2 (en) 2002-03-19 2003-10-21 International Business Machines Corporation Strained fin FETs structure and method
US6605498B1 (en) 2002-03-29 2003-08-12 Intel Corporation Semiconductor transistor having a backfilled channel material
US6784076B2 (en) 2002-04-08 2004-08-31 Micron Technology, Inc. Process for making a silicon-on-insulator ledge by implanting ions from silicon source
FR2838238B1 (fr) 2002-04-08 2005-04-15 St Microelectronics Sa Dispositif semiconducteur a grille enveloppante encapsule dans un milieu isolant
US6762469B2 (en) 2002-04-19 2004-07-13 International Business Machines Corporation High performance CMOS device structure with mid-gap metal gate
US6713396B2 (en) 2002-04-29 2004-03-30 Hewlett-Packard Development Company, L.P. Method of fabricating high density sub-lithographic features on a substrate
US6537885B1 (en) 2002-05-09 2003-03-25 Infineon Technologies Ag Transistor and method of manufacturing a transistor having a shallow junction formation using a two step EPI layer
US6642090B1 (en) 2002-06-03 2003-11-04 International Business Machines Corporation Fin FET devices from bulk semiconductor and method for forming
US7074623B2 (en) 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US6680240B1 (en) 2002-06-25 2004-01-20 Advanced Micro Devices, Inc. Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide
US7105891B2 (en) 2002-07-15 2006-09-12 Texas Instruments Incorporated Gate structure and method
US6974729B2 (en) 2002-07-16 2005-12-13 Interuniversitair Microelektronica Centrum (Imec) Integrated semiconductor fin device and a method for manufacturing such device
KR100477543B1 (ko) 2002-07-26 2005-03-18 동부아남반도체 주식회사 단채널 트랜지스터 형성방법
US6919238B2 (en) 2002-07-29 2005-07-19 Intel Corporation Silicon on insulator (SOI) transistor and methods of fabrication
US6921702B2 (en) 2002-07-30 2005-07-26 Micron Technology Inc. Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
EP1387395B1 (en) 2002-07-31 2016-11-23 Micron Technology, Inc. Method for manufacturing semiconductor integrated circuit structures
JP2004071996A (ja) 2002-08-09 2004-03-04 Hitachi Ltd 半導体集積回路装置の製造方法
US6891234B1 (en) 2004-01-07 2005-05-10 Acorn Technologies, Inc. Transistor with workfunction-induced charge layer
US6984585B2 (en) 2002-08-12 2006-01-10 Applied Materials Inc Method for removal of residue from a magneto-resistive random access memory (MRAM) film stack using a sacrificial mask layer
US6833556B2 (en) 2002-08-12 2004-12-21 Acorn Technologies, Inc. Insulated gate field effect transistor having passivated schottky barriers to the channel
JP3865233B2 (ja) 2002-08-19 2007-01-10 富士通株式会社 Ｃｍｏｓ集積回路装置
US7358121B2 (en) 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US7163851B2 (en) 2002-08-26 2007-01-16 International Business Machines Corporation Concurrent Fin-FET and thick-body device fabrication
JP5179692B2 (ja) 2002-08-30 2013-04-10 富士通セミコンダクター株式会社 半導体記憶装置及びその製造方法
US6770516B2 (en) 2002-09-05 2004-08-03 Taiwan Semiconductor Manufacturing Company Method of forming an N channel and P channel FINFET device on the same semiconductor substrate
JP3651802B2 (ja) 2002-09-12 2005-05-25 株式会社東芝 半導体装置の製造方法
US6794313B1 (en) 2002-09-20 2004-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Oxidation process to improve polysilicon sidewall roughness
JP3556651B2 (ja) 2002-09-27 2004-08-18 沖電気工業株式会社 半導体装置の製造方法
US6800910B2 (en) 2002-09-30 2004-10-05 Advanced Micro Devices, Inc. FinFET device incorporating strained silicon in the channel region
KR100481209B1 (ko) 2002-10-01 2005-04-08 삼성전자주식회사 다중 채널을 갖는 모스 트랜지스터 및 그 제조방법
JP4294935B2 (ja) 2002-10-17 2009-07-15 株式会社ルネサステクノロジ 半導体装置
US6833588B2 (en) 2002-10-22 2004-12-21 Advanced Micro Devices, Inc. Semiconductor device having a U-shaped gate structure
US6706571B1 (en) 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
US6706581B1 (en) 2002-10-29 2004-03-16 Taiwan Semiconductor Manufacturing Company Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices
US6787439B2 (en) 2002-11-08 2004-09-07 Advanced Micro Devices, Inc. Method using planarizing gate material to improve gate critical dimension in semiconductor devices
US6611029B1 (en) 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates
US6709982B1 (en) 2002-11-26 2004-03-23 Advanced Micro Devices, Inc. Double spacer FinFET formation
US6855990B2 (en) 2002-11-26 2005-02-15 Taiwan Semiconductor Manufacturing Co., Ltd Strained-channel multiple-gate transistor
US6825506B2 (en) 2002-11-27 2004-11-30 Intel Corporation Field effect transistor and method of fabrication
US6821834B2 (en) 2002-12-04 2004-11-23 Yoshiyuki Ando Ion implantation methods and transistor cell layout for fin type transistors
KR100487922B1 (ko) 2002-12-06 2005-05-06 주식회사 하이닉스반도체 반도체소자의 트랜지스터 및 그 형성방법
US7214991B2 (en) 2002-12-06 2007-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. CMOS inverters configured using multiple-gate transistors
US7728360B2 (en) 2002-12-06 2010-06-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple-gate transistor structure
US6645797B1 (en) 2002-12-06 2003-11-11 Advanced Micro Devices, Inc. Method for forming fins in a FinFET device using sacrificial carbon layer
US6686231B1 (en) 2002-12-06 2004-02-03 Advanced Micro Devices, Inc. Damascene gate process with sacrificial oxide in semiconductor devices
US6869868B2 (en) 2002-12-13 2005-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a MOSFET device with metal containing gate structures
US6867425B2 (en) 2002-12-13 2005-03-15 Intel Corporation Lateral phase change memory and method therefor
US6794718B2 (en) 2002-12-19 2004-09-21 International Business Machines Corporation High mobility crystalline planes in double-gate CMOS technology
WO2004059726A1 (en) 2002-12-20 2004-07-15 International Business Machines Corporation Integrated antifuse structure for finfet and cmos devices
US6780694B2 (en) 2003-01-08 2004-08-24 International Business Machines Corporation MOS transistor
US7259425B2 (en) 2003-01-23 2007-08-21 Advanced Micro Devices, Inc. Tri-gate and gate around MOSFET devices and methods for making same
US6762483B1 (en) 2003-01-23 2004-07-13 Advanced Micro Devices, Inc. Narrow fin FinFET
US6803631B2 (en) 2003-01-23 2004-10-12 Advanced Micro Devices, Inc. Strained channel finfet
US6885055B2 (en) 2003-02-04 2005-04-26 Lee Jong-Ho Double-gate FinFET device and fabricating method thereof
KR100543472B1 (ko) 2004-02-11 2006-01-20 삼성전자주식회사 소오스/드레인 영역에 디플리션 방지막을 구비하는 반도체소자 및 그 형성 방법
US7304336B2 (en) 2003-02-13 2007-12-04 Massachusetts Institute Of Technology FinFET structure and method to make the same
US6855606B2 (en) 2003-02-20 2005-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-rod devices
US7105894B2 (en) 2003-02-27 2006-09-12 Taiwan Semiconductor Manufacturing Co., Ltd. Contacts to semiconductor fin devices
KR100499159B1 (ko) 2003-02-28 2005-07-01 삼성전자주식회사 리세스 채널을 갖는 반도체장치 및 그 제조방법
US6716690B1 (en) 2003-03-12 2004-04-06 Advanced Micro Devices, Inc. Uniformly doped source/drain junction in a double-gate MOSFET
US6800885B1 (en) 2003-03-12 2004-10-05 Advance Micro Devices, Inc. Asymmetrical double gate or all-around gate MOSFET devices and methods for making same
US6787854B1 (en) 2003-03-12 2004-09-07 Advanced Micro Devices, Inc. Method for forming a fin in a finFET device
TW582099B (en) 2003-03-13 2004-04-01 Ind Tech Res Inst Method of adhering material layer on transparent substrate and method of forming single crystal silicon on transparent substrate
JP4563652B2 (ja) 2003-03-13 2010-10-13 シャープ株式会社 メモリ機能体および微粒子形成方法並びにメモリ素子、半導体装置および電子機器
US6844238B2 (en) 2003-03-26 2005-01-18 Taiwan Semiconductor Manufacturing Co., Ltd Multiple-gate transistors with improved gate control
US20040191980A1 (en) 2003-03-27 2004-09-30 Rafael Rios Multi-corner FET for better immunity from short channel effects
US6790733B1 (en) 2003-03-28 2004-09-14 International Business Machines Corporation Preserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer
US6764884B1 (en) 2003-04-03 2004-07-20 Advanced Micro Devices, Inc. Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device
US6902962B2 (en) 2003-04-04 2005-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Silicon-on-insulator chip with multiple crystal orientations
TWI231994B (en) 2003-04-04 2005-05-01 Univ Nat Taiwan Strained Si FinFET
US7442415B2 (en) 2003-04-11 2008-10-28 Sharp Laboratories Of America, Inc. Modulated temperature method of atomic layer deposition (ALD) of high dielectric constant films
JP2004319704A (ja) 2003-04-15 2004-11-11 Seiko Instruments Inc 半導体装置
US6888179B2 (en) 2003-04-17 2005-05-03 Bae Systems Information And Electronic Systems Integration Inc GaAs substrate with Sb buffering for high in devices
TW200506093A (en) 2003-04-21 2005-02-16 Aviza Tech Inc System and method for forming multi-component films
WO2004097943A1 (ja) 2003-04-28 2004-11-11 Matsushita Electric Industrial Co., Ltd. 半導体装置とその製造方法
US6867433B2 (en) 2003-04-30 2005-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
JP3976703B2 (ja) 2003-04-30 2007-09-19 エルピーダメモリ株式会社 半導体装置の製造方法
US20040219711A1 (en) 2003-04-30 2004-11-04 Bi-Chu Wu Method for manufacturing a polymer chip and an integrated mold for the same
US6838322B2 (en) 2003-05-01 2005-01-04 Freescale Semiconductor, Inc. Method for forming a double-gated semiconductor device
WO2004107452A1 (ja) 2003-05-30 2004-12-09 Matsushita Electric Industrial Co., Ltd. 半導体装置およびその製造方法
US6830998B1 (en) 2003-06-17 2004-12-14 Advanced Micro Devices, Inc. Gate dielectric quality for replacement metal gate transistors
US7045401B2 (en) 2003-06-23 2006-05-16 Sharp Laboratories Of America, Inc. Strained silicon finFET device
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US20040262683A1 (en) 2003-06-27 2004-12-30 Bohr Mark T. PMOS transistor strain optimization with raised junction regions
US6909151B2 (en) 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US6960517B2 (en) 2003-06-30 2005-11-01 Intel Corporation N-gate transistor
US6716686B1 (en) 2003-07-08 2004-04-06 Advanced Micro Devices, Inc. Method for forming channels in a finfet device
US6921982B2 (en) 2003-07-21 2005-07-26 International Business Machines Corporation FET channel having a strained lattice structure along multiple surfaces
US7013447B2 (en) 2003-07-22 2006-03-14 Freescale Semiconductor, Inc. Method for converting a planar transistor design to a vertical double gate transistor design
KR100487566B1 (ko) 2003-07-23 2005-05-03 삼성전자주식회사 핀 전계 효과 트랜지스터 및 그 형성 방법
KR100487567B1 (ko) 2003-07-24 2005-05-03 삼성전자주식회사 핀 전계효과 트랜지스터 형성 방법
EP1519420A2 (en) 2003-09-25 2005-03-30 Interuniversitaire Microelectronica Centrum vzw ( IMEC) Multiple gate semiconductor device and method for forming same
US6835618B1 (en) 2003-08-05 2004-12-28 Advanced Micro Devices, Inc. Epitaxially grown fin for FinFET
US7172943B2 (en) 2003-08-13 2007-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-gate transistors formed on bulk substrates
KR100496891B1 (ko) 2003-08-14 2005-06-23 삼성전자주식회사 핀 전계효과 트랜지스터를 위한 실리콘 핀 및 그 제조 방법
US7355253B2 (en) 2003-08-22 2008-04-08 International Business Machines Corporation Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates
JPWO2005022637A1 (ja) 2003-08-28 2007-11-01 日本電気株式会社 フィン型電界効果トランジスタを有する半導体装置
US6998301B1 (en) 2003-09-03 2006-02-14 Advanced Micro Devices, Inc. Method for forming a tri-gate MOSFET
US6877728B2 (en) 2003-09-04 2005-04-12 Lakin Manufacturing Corporation Suspension assembly having multiple torsion members which cooperatively provide suspension to a wheel
JP4439358B2 (ja) 2003-09-05 2010-03-24 株式会社東芝 電界効果トランジスタ及びその製造方法
JP3855061B2 (ja) 2003-09-08 2006-12-06 独立行政法人情報通信研究機構 Ｓｉ基板上への化合物半導体薄膜形成方法
US7170126B2 (en) 2003-09-16 2007-01-30 International Business Machines Corporation Structure of vertical strained silicon devices
US7242041B2 (en) * 2003-09-22 2007-07-10 Lucent Technologies Inc. Field-effect transistors with weakly coupled layered inorganic semiconductors
US6970373B2 (en) 2003-10-02 2005-11-29 Intel Corporation Method and apparatus for improving stability of a 6T CMOS SRAM cell
US7612416B2 (en) 2003-10-09 2009-11-03 Nec Corporation Semiconductor device having a conductive portion below an interlayer insulating film and method for producing the same
EP1683193A1 (en) 2003-10-22 2006-07-26 Spinnaker Semiconductor, Inc. Dynamic schottky barrier mosfet device and method of manufacture
US6946377B2 (en) 2003-10-29 2005-09-20 Texas Instruments Incorporated Multiple-gate MOSFET device with lithography independent silicon body thickness and methods for fabricating the same
US7138320B2 (en) 2003-10-31 2006-11-21 Advanced Micro Devices, Inc. Advanced technique for forming a transistor having raised drain and source regions
KR100515061B1 (ko) 2003-10-31 2005-09-14 삼성전자주식회사 핀 전계 효과 트랜지스터를 갖는 반도체 소자 및 그 형성방법
US6867460B1 (en) 2003-11-05 2005-03-15 International Business Machines Corporation FinFET SRAM cell with chevron FinFET logic
US6885072B1 (en) 2003-11-18 2005-04-26 Applied Intellectual Properties Co., Ltd. Nonvolatile memory with undercut trapping structure
US7545001B2 (en) 2003-11-25 2009-06-09 Taiwan Semiconductor Manufacturing Company Semiconductor device having high drive current and method of manufacture therefor
US7183137B2 (en) 2003-12-01 2007-02-27 Taiwan Semiconductor Manufacturing Company Method for dicing semiconductor wafers
US7075150B2 (en) 2003-12-02 2006-07-11 International Business Machines Corporation Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique
US7018551B2 (en) 2003-12-09 2006-03-28 International Business Machines Corporation Pull-back method of forming fins in FinFets
US7388258B2 (en) 2003-12-10 2008-06-17 International Business Machines Corporation Sectional field effect devices
JP2005183770A (ja) 2003-12-22 2005-07-07 Mitsubishi Electric Corp 高周波用半導体装置
US7569882B2 (en) 2003-12-23 2009-08-04 Interuniversitair Microelektronica Centrum (Imec) Non-volatile multibit memory cell and method of manufacturing thereof
US7662689B2 (en) 2003-12-23 2010-02-16 Intel Corporation Strained transistor integration for CMOS
US7223679B2 (en) 2003-12-24 2007-05-29 Intel Corporation Transistor gate electrode having conductor material layer
US7247578B2 (en) 2003-12-30 2007-07-24 Intel Corporation Method of varying etch selectivities of a film
US7078282B2 (en) 2003-12-30 2006-07-18 Intel Corporation Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films
US7045407B2 (en) 2003-12-30 2006-05-16 Intel Corporation Amorphous etch stop for the anisotropic etching of substrates
US7005333B2 (en) 2003-12-30 2006-02-28 Infineon Technologies Ag Transistor with silicon and carbon layer in the channel region
US7105390B2 (en) 2003-12-30 2006-09-12 Intel Corporation Nonplanar transistors with metal gate electrodes
US7705345B2 (en) 2004-01-07 2010-04-27 International Business Machines Corporation High performance strained silicon FinFETs device and method for forming same
US6974736B2 (en) 2004-01-09 2005-12-13 International Business Machines Corporation Method of forming FET silicide gate structures incorporating inner spacers
US7056794B2 (en) 2004-01-09 2006-06-06 International Business Machines Corporation FET gate structure with metal gate electrode and silicide contact
US7268058B2 (en) 2004-01-16 2007-09-11 Intel Corporation Tri-gate transistors and methods to fabricate same
US7385247B2 (en) 2004-01-17 2008-06-10 Samsung Electronics Co., Ltd. At least penta-sided-channel type of FinFET transistor
JP2005209782A (ja) 2004-01-21 2005-08-04 Toshiba Corp 半導体装置
US7250645B1 (en) 2004-01-22 2007-07-31 Advanced Micro Devices, Inc. Reversed T-shaped FinFET
US7224029B2 (en) 2004-01-28 2007-05-29 International Business Machines Corporation Method and structure to create multiple device widths in FinFET technology in both bulk and SOI
KR100587672B1 (ko) 2004-02-02 2006-06-08 삼성전자주식회사 다마신 공법을 이용한 핀 트랜지스터 형성방법
EP1566844A3 (en) 2004-02-20 2006-04-05 Samsung Electronics Co., Ltd. Multi-gate transistor and method for manufacturing the same
US7060539B2 (en) 2004-03-01 2006-06-13 International Business Machines Corporation Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby
JP4852694B2 (ja) 2004-03-02 2012-01-11 独立行政法人産業技術総合研究所 半導体集積回路およびその製造方法
US6921691B1 (en) 2004-03-18 2005-07-26 Infineon Technologies Ag Transistor with dopant-bearing metal in source and drain
JPWO2005091374A1 (ja) 2004-03-19 2008-02-07 日本電気株式会社 半導体装置及びその製造方法
KR100576361B1 (ko) 2004-03-23 2006-05-03 삼성전자주식회사 3차원 시모스 전계효과 트랜지스터 및 그것을 제조하는 방법
US7141480B2 (en) 2004-03-26 2006-11-28 Texas Instruments Incorporated Tri-gate low power device and method for manufacturing the same
US8450806B2 (en) 2004-03-31 2013-05-28 International Business Machines Corporation Method for fabricating strained silicon-on-insulator structures and strained silicon-on insulator structures formed thereby
US7154118B2 (en) 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US20050224797A1 (en) 2004-04-01 2005-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS fabricated on different crystallographic orientation substrates
US20050230763A1 (en) 2004-04-15 2005-10-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a microelectronic device with electrode perturbing sill
KR100642632B1 (ko) 2004-04-27 2006-11-10 삼성전자주식회사 반도체소자의 제조방법들 및 그에 의해 제조된 반도체소자들
US7915443B2 (en) 2006-11-16 2011-03-29 Allergan, Inc. Sulfoximines as kinase inhibitors
US7084018B1 (en) 2004-05-05 2006-08-01 Advanced Micro Devices, Inc. Sacrificial oxide for minimizing box undercut in damascene FinFET
US20050255642A1 (en) 2004-05-11 2005-11-17 Chi-Wen Liu Method of fabricating inlaid structure
US6864540B1 (en) 2004-05-21 2005-03-08 International Business Machines Corp. High performance FET with elevated source/drain region
KR100625177B1 (ko) 2004-05-25 2006-09-20 삼성전자주식회사 멀티-브리지 채널형 모오스 트랜지스터의 제조 방법
US6955961B1 (en) 2004-05-27 2005-10-18 Macronix International Co., Ltd. Method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution
KR100634372B1 (ko) 2004-06-04 2006-10-16 삼성전자주식회사 반도체 소자들 및 그 형성 방법들
US7132360B2 (en) 2004-06-10 2006-11-07 Freescale Semiconductor, Inc. Method for treating a semiconductor surface to form a metal-containing layer
WO2005122276A1 (ja) 2004-06-10 2005-12-22 Nec Corporation 半導体装置及びその製造方法
US7452778B2 (en) 2004-06-10 2008-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-wire devices and methods of fabrication
US7291886B2 (en) 2004-06-21 2007-11-06 International Business Machines Corporation Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs
US7413957B2 (en) 2004-06-24 2008-08-19 Applied Materials, Inc. Methods for forming a transistor
KR100541657B1 (ko) 2004-06-29 2006-01-11 삼성전자주식회사 멀티 게이트 트랜지스터의 제조방법 및 이에 의해 제조된멀티 게이트 트랜지스터
US8669145B2 (en) 2004-06-30 2014-03-11 International Business Machines Corporation Method and structure for strained FinFET devices
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US20060040054A1 (en) 2004-08-18 2006-02-23 Pearlstein Ronald M Passivating ALD reactor chamber internal surfaces to prevent residue buildup
US20060043500A1 (en) 2004-08-24 2006-03-02 Jian Chen Transistor structure with stress modification and capacitive reduction feature in a channel direction and method thereof
US7105934B2 (en) 2004-08-30 2006-09-12 International Business Machines Corporation FinFET with low gate capacitance and low extrinsic resistance
US7250367B2 (en) 2004-09-01 2007-07-31 Micron Technology, Inc. Deposition methods using heteroleptic precursors
US7071064B2 (en) 2004-09-23 2006-07-04 Intel Corporation U-gate transistors and methods of fabrication
US7332439B2 (en) 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US20060148182A1 (en) * 2005-01-03 2006-07-06 Suman Datta Quantum well transistor using high dielectric constant dielectric layer
US7247547B2 (en) 2005-01-05 2007-07-24 International Business Machines Corporation Method of fabricating a field effect transistor having improved junctions
US7875547B2 (en) 2005-01-12 2011-01-25 Taiwan Semiconductor Manufacturing Co., Ltd. Contact hole structures and contact structures and fabrication methods thereof
US7470951B2 (en) 2005-01-31 2008-12-30 Freescale Semiconductor, Inc. Hybrid-FET and its application as SRAM
US20060172480A1 (en) 2005-02-03 2006-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. Single metal gate CMOS device design
US20060180859A1 (en) 2005-02-16 2006-08-17 Marko Radosavljevic Metal gate carbon nanotube transistor
DE102005008478B3 (de) 2005-02-24 2006-10-26 Infineon Technologies Ag Verfahren zur Herstellung von sublithographischen Strukturen
US7238564B2 (en) 2005-03-10 2007-07-03 Taiwan Semiconductor Manufacturing Company Method of forming a shallow trench isolation structure
JP4825526B2 (ja) 2005-03-28 2011-11-30 株式会社東芝 Ｆｉｎ型チャネルトランジスタおよびその製造方法
US7177177B2 (en) 2005-04-07 2007-02-13 International Business Machines Corporation Back-gate controlled read SRAM cell
KR100699839B1 (ko) 2005-04-21 2007-03-27 삼성전자주식회사 다중채널을 갖는 반도체 장치 및 그의 제조방법.
US7429536B2 (en) 2005-05-23 2008-09-30 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7319074B2 (en) 2005-06-13 2008-01-15 United Microelectronics Corp. Method of defining polysilicon patterns
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US20070023795A1 (en) 2005-07-15 2007-02-01 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
US7348642B2 (en) 2005-08-03 2008-03-25 International Business Machines Corporation Fin-type field effect transistor
US7352034B2 (en) 2005-08-25 2008-04-01 International Business Machines Corporation Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures
US7339241B2 (en) 2005-08-31 2008-03-04 Freescale Semiconductor, Inc. FinFET structure with contacts
US7416943B2 (en) 2005-09-01 2008-08-26 Micron Technology, Inc. Peripheral gate stacks and recessed array gates
US20070069302A1 (en) 2005-09-28 2007-03-29 Been-Yih Jin Method of fabricating CMOS devices having a single work function gate electrode by band gap engineering and article made thereby
US20070090416A1 (en) 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US7479421B2 (en) 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US8513066B2 (en) 2005-10-25 2013-08-20 Freescale Semiconductor, Inc. Method of making an inverted-T channel transistor
KR100718159B1 (ko) 2006-05-18 2007-05-14 삼성전자주식회사 와이어-타입 반도체 소자 및 그 제조 방법
US20080017890A1 (en) 2006-06-30 2008-01-24 Sandisk 3D Llc Highly dense monolithic three dimensional memory array and method for forming
US7573059B2 (en) 2006-08-02 2009-08-11 Intel Corporation Dislocation-free InSb quantum well structure on Si using novel buffer architecture
US7456471B2 (en) 2006-09-15 2008-11-25 International Business Machines Corporation Field effect transistor with raised source/drain fin straps
US7646046B2 (en) 2006-11-14 2010-01-12 Infineon Technologies Ag Field effect transistor with a fin structure
US7678632B2 (en) 2006-11-17 2010-03-16 Infineon Technologies Ag MuGFET with increased thermal mass
US7655989B2 (en) 2006-11-30 2010-02-02 International Business Machines Corporation Triple gate and double gate finFETs with different vertical dimension fins
US20080128797A1 (en) 2006-11-30 2008-06-05 International Business Machines Corporation Structure and method for multiple height finfet devices
US20080212392A1 (en) 2007-03-02 2008-09-04 Infineon Technologies Multiple port mugfet sram
JP4406439B2 (ja) 2007-03-29 2010-01-27 株式会社東芝 半導体装置の製造方法

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
Ashley T. et al.Novel InSb-based quantum well transistors for ultra-high speed
Ashley, T. et al.Novel InSb-based quantum well transistors for ultra-high speed, low power logic applications.《Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on》.2004,第3卷2253-2256. *
Frank MM et al.HfO2 and Al2O3 gate dielectrics on GaAs grown by atomic layer deposition.《APPLIED PHYSICS LETTERS》.2005,第86卷(第15期),152904-1～152904-3. *
JP特开平6-132521A 1994.05.13

Also Published As

Publication number Publication date
ATE521983T1 (de) 2011-09-15
US7989280B2 (en) 2011-08-02
US7485503B2 (en) 2009-02-03
EP2273538A3 (en) 2011-03-02
EP2273538B1 (en) 2012-09-26
EP1955366B1 (en) 2011-08-24
TWI335625B (en) 2011-01-01
CN101341583A (zh) 2009-01-07
EP2273538A2 (en) 2011-01-12
US20090095984A1 (en) 2009-04-16
EP1955366A1 (en) 2008-08-13
US20070123003A1 (en) 2007-05-31
WO2007064492A1 (en) 2007-06-07
TW200735216A (en) 2007-09-16

Similar Documents

Publication Publication Date Title
CN101341583B (zh) Ⅲ-ⅴ族半导体器件的电介质界面
US8344418B2 (en) Materials for interfacing high-K dielectric layers with III-V semiconductors
Yatabe et al. Insulated gate and surface passivation structures for GaN-based power transistors
JP5341020B2 (ja) 傾斜三元または四元マルチゲートトランジスタ
US8247796B2 (en) Semiconductor device
KR101194465B1 (ko) 실리콘 상에 버퍼층 아키텍쳐를 형성하는 방법 및 그에 의해 형성된 구조물
US9660063B2 (en) Semiconductor structure having sets of III-V compound layers and method of forming the same
CN107464843B (zh) 半导体结构、hemt结构及其形成方法
US9064946B1 (en) III-V FET device with overlapped extension regions using gate last
JP2010182750A (ja) Ｉｉｉ−ｖ族化合物半導体素子
CN107026198B (zh) 半导体结构及其制造方法
JP2009026975A (ja) 半導体装置
US8232581B2 (en) Method for manufacturing an III-V engineered substrate and the III-V engineered substrate thereof
TWI599000B (zh) 用於半導體裝置之無定形結晶過渡材料及其形成方法
TW200818335A (en) Gate dielectric materials for group III-V enhancement mode transistors
US20130267077A1 (en) Method and system for manufacturing semiconductor device
KR102079177B1 (ko) 하프늄 옥시나이트라이트 막의 형성 방법 및 이를 이용한 반도체 소자
JP7177398B2 (ja) 高電子移動度トランジスタ
US20210193820A1 (en) Semiconductor structure and forming method thereof
EP4117041A1 (en) Semiconductor structure with barrier layer comprising indium aluminium nitride and method of growing thereof
Maeda et al. Two-Dimensional Electron Gas Transport Properties in AlGaN/GaN Heterostructure Field-Effect Transistors
Chan Indium Gallium Arsenide Three-State and Non-Volatile Memory Quantum Dot Devices
Gourab et al. Strategic review of arsenide, phosphide and nitride mosfets
Dutta et al. Strategic Review of Arsenide, Phosphide and Nitride MOSFETs

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20111214

Termination date: 20191117