CN101292346A - 在块状衬底上集成平面型与非平面型cmos晶体管的工艺及用此工艺制作的器件 - Google Patents

在块状衬底上集成平面型与非平面型cmos晶体管的工艺及用此工艺制作的器件 Download PDF

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CN101292346A
CN101292346A CNA2006800355214A CN200680035521A CN101292346A CN 101292346 A CN101292346 A CN 101292346A CN A2006800355214 A CNA2006800355214 A CN A2006800355214A CN 200680035521 A CN200680035521 A CN 200680035521A CN 101292346 A CN101292346 A CN 101292346A
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active area
sidewall
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J·卡瓦利罗斯
J·布拉斯克
B·多伊尔
U·沙
S·达塔
M·多奇
M·梅茨
R·仇
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Intel Corp
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Abstract

一种能够将平面型(10)和非平面型(20、30)晶体管集成在块状半导体衬底上的工艺，其中，所有晶体管的沟道可在连续的宽度范围加以限定。

Description

在块状衬底上集成平面型与非平面型CMOS晶体管的工艺及用此工艺制作的器件
技术领域
[0001]本发明涉及半导体集成电路制造领域，更具体地，涉及将带有可变沟道宽度的非平面型晶体管结合到块状半导体CMOS工艺中的方法。
背景技术
[0002]几十年来，平面型晶体管一直在块状半导体衬底上制作。图1A所示的晶体管100就是这样的一种平面型器件。具有相对的侧壁106、107和顶面108的有源区形成在块状半导体衬底101上的绝缘区110之间。
绝缘区110基本上覆盖相对的侧壁106和107。顶部半导体表面108划分成源区116、漏区117和由栅绝缘层112以及栅电极113覆盖的沟道区。在平面型晶体管设计中，器件一般通过顶部半导体表面108和栅电极113之间的电容耦合来控制(即栅控)。因为沟道由单个栅电极-半导体界面栅控，所以平面型晶体管常称为单栅极器件。
[0003]近来，非平面型晶体管已经在改进方案之内，以致力于解决影响平面型纳米级晶体管的短沟道效应(Short Channel Effect)(SCE)。非平面型晶体管的半导体沟道是非平面型的，并且栅电极经由多于一个的表面耦合到沟道，一般经由非平面地形成的侧壁部分。图1B所示的晶体管150就是这样一种非平面型器件。有源半导体区具有相对的侧壁106、107和顶面108，形成在包含载体102上的绝缘区103的衬底上。顶面108和相对的侧壁106、107划分成源区116、漏区117和由栅绝缘层112及栅电极113覆盖的沟道区。该晶体管设计成能够由相对的侧壁106、107及器件的顶面108栅控(减小SCE效应)。因为沟道由多个栅电极-半导体界面来栅控，非平面型晶体管常称为多栅极器件。
[0004]非平面型器件即多栅极器件已经一般形成在包含绝缘层的衬底上，通常称为绝缘层上半导体(semiconductor-on-insulator)(SOI)。尽管形成在SOI上的非平面型器件在有许多优点，同时也存在许多缺点。例如，SOI上的非平面型晶体管的沟道宽度，由形成在SOI衬底上的绝缘区的有源硅层(active silicon layer)的最终厚度限制。因此，电路设计者受限于一个基本宽度，而对于形成在衬底上的电路的所有晶体管而言，就是该宽度的许多倍。如图1C所示，多个非平面体(每个都具有源区116和漏区117)，通过共同的栅电极113经由栅绝缘层112并行地电耦合而形成器件175。器件175限制了电路设计灵活性，因为载流宽度只能离散地增加，而不是连续地增加。相对于传统的平面型晶体管，还因为光刻节距的限制，非平面型晶体管如器件175(如图1C所示)将招致版图设计惩罚(layout penalty)。形成在SOI上的器件的另一缺点是公知的″浮体″(“floating body”)效应，该效应由埋入的绝缘层引起，它会造成用于晶体管的接地平面(ground plane)的损失。另外，与形成在体衬底上的器件相比，形成在SOI衬底上的非平面型晶体管的导热率会变差且总成本会增加。
附图说明
[0005]图1A是说明在块状半导体衬底上形成的传统平面型单栅晶体管的透视图，图1B是说明在SOI衬底上形成的传统非平面型多栅晶体管的透视图。
[0006]图2是说明本发明实施例的电路器件的透视图，该电路器件具有平面型晶体管和非平面型晶体管。
[0007]图3A-3G是说明本发明实施例的制作具有平面型和非平面型晶体管的器件的方法的透视图。
具体实施方式
[0008]介绍了一种新颖的CMOS器件结构和制作该器件的方法。在下面的说明中，阐明了许多具体细节，诸如具体材料、尺寸和工艺等，以提供对本发明的彻底理解。其它的实例中，没有特别详细的介绍公知的半导体工艺和制造业工艺方法，以避免不必要地使本发明变得模糊。
[0009]根据图2所示的本发明的实施例，三个晶体管(平面型器件10、具有第一沟道宽度的非平面型器件20和具有第二沟道的非平面型器件30)形成在单个″块状半导体″衬底201上。晶体管10、20和30各自结合到半导体衬底上(防止浮体效应)，且平面型晶体管设计和非平面型晶体管设计都具有能够独立限定为任何值(而不是仅仅离散值)的沟道宽度。通过使得非平面型晶体管20、30具有不同的侧壁高度的方法，能够规定不同的沟道宽度，且单个器件的个别部分的性能要求能够通过平面型晶体管(具有基本的SCE效应)和非平面型晶体管(具有减少的SCE效应)的任何组合来个别满足。在本发明的特定实施例中，微处理器核(包括逻辑区)由平面型晶体管制成，而微处理器的高速缓冲存储器(包括如SRAM等存储器)由非平面型晶体管制成。在本发明的另一特定实施例中，需要大的总电流的电路部分(诸如驱动器部分)由平面型晶体管制成，平面型晶体管的载流沟道宽度大于用于电路其它部分的非平面型晶体管的沟道宽度。
[0010]本发明的非平面型晶体管的实施例包括但不限于双栅、FinFET、三栅、pi-栅或omega-栅设计。在一些实施例中，所有非平面型晶体管是具有顶栅极的″三栅″设计，而在其它的实施例中所有非平面型晶体管是仅有侧壁栅极的″双栅″设计。
[0011]衬底201由″块状半导体″构成，诸如(但不限于)单晶硅衬底或砷化镓衬底。在本发明另一实施例中，衬底201是体硅半导体，该体硅半导体具有掺杂的外延硅层，该外延硅层带有杂质浓度水平在1x1016-1x1019原子/cm3之间，具有p导电型或者n导电型。在本发明另一实施例中，衬底201是具有未掺杂的即本征的外延硅层的体硅半导体衬底。在″块状半导体″衬底中，不像SOI衬底，在用于制作有源器件半导体部分和用于处置(handling)的半导体部分之间没有″埋入″的绝缘层。
[0012]如图2所示，晶体管10、20和30包括在块状半导体衬底上的有源区204、224和244。绝缘区210之间的距离限定单个晶体管有源区宽度。有源区204、224、244分别具有顶面218、238、258和底面208、228、248。如图2所示，底面208、228和248限定为与绝缘区210底部表面基本上齐平。为了说明的简洁，将图2的半导体有源区说成是在衬底″之上″，而衬底是半导体在基准平面208、228和248以下的部分。然而，如果选定不同的基准平面，还可以认为有源区在衬底″之中″。有源区侧壁部分露出于栅绝缘层，而控制栅电极被称为″栅耦合侧壁″(gate-coupled sidewall)。如图2所示，绝缘区210基本上覆盖晶体管10的有源区204的侧壁206和207。因此，平面型单栅晶体管10不具有栅耦合侧壁，因为顶面218和底面208之间的距离大致等于绝缘区210的边界厚度。同样地，晶体管10的有源区仅仅主要是耦合于控制栅极213的顶面218，并且沟道宽度等于顶面218的宽度。然而对于非平面型器件20，在相邻绝缘区210顶面上延伸的侧壁对226、227部分是″栅耦合″的，这部分对器件20的整个沟道宽度有贡献。如图2所示，晶体管20的″栅耦合侧壁″高度等于顶面238和底面228之间的距离减去相邻绝缘区210的厚度。在本发明的实施例中，如图2的晶体管30中所示，栅耦合侧壁的高度基本上等于顶面258有源区的宽度。在本发明另一实施例中，非平面型晶体管栅耦合侧壁高度在一半有源区宽度和两倍有源区宽度之间。在本发明的一个特定实施例中，非平面型晶体管具有的有源区宽度和栅耦合侧壁高度小于30纳米，更具体地说，小于20纳米。
[0013]本发明实施例的非平面型晶体管的载流宽度，实际上能够通过改变栅耦合侧壁高度而连续地和个别地设置到任何所希望的值。如图2中所述，晶体管20的侧壁226、227具有第一栅耦合侧壁高度，而晶体管30的侧壁246、247具有不同的第二栅耦合侧壁高度。因此，晶体管20具有第一载流沟道宽度，而晶体管30具有不同的第二载流沟道宽度。因为当栅耦合侧壁高度增加时，非平面型晶体管的载流沟道宽度增加，在如图2所示实施例中，晶体管20具有的沟道宽度大于晶体管30的沟道宽度。因此，本发明的实施例具有沟道宽度连续可变化的非平面型晶体管，由此可提供以前的非平面型晶体管所难以获得的电路设计灵活性。
[0014]在本发明实施例中，对于具有沟道宽度大于最小宽度的非平面型晶体管，没有招致版图设计效率惩罚(layout efficiency penalty)。设计效率是非平面型器件设计的绝对载流宽度与占有相同的设计宽度的典型平面型器件的绝对载流宽度的比值。在本发明实施例的中，单个非平面型晶体管的栅耦合侧壁的高度设定为可提供所希望的全部载流宽度。因此，载流宽度的设定不依赖于具有离散沟道宽度的平行非平面型器件的数量的增加。因为沟道宽度随着侧壁高度而不是顶面面积而增加，所以不需要另外的设计宽度来增加根据本发明的特定实施例制作的非平面型晶体管的沟道宽度。如此，这些特定实施例提高了器件的组装密度，并可具有大于单一元件(unity)的版图设计效率。
[0015]如图2所示，晶体管10、20和30具有栅绝缘层212。在所述的非平面型实施例中，栅绝缘层212包围有源区，与露出的半导体表面相接触。在这些实施例中，栅介质层212与晶体管20、30有源区的侧壁及顶面接触，如图2所示。在其它的实施例中，诸如特殊的FinFET或双栅设计中，栅电介质层仅与有源区的侧壁接触，而不与非平面型器件顶面238、258接触。在平面型晶体管实施例中，诸如在图2中的晶体管10，栅绝缘层仅仅形成在顶面218上。栅绝缘层212可为任何公知的、与半导体表面和栅电极213相容的介质材料。在本发明的实施例中，栅介质层是二氧化硅(SiO2)、氮氧化硅(SiOxNy)或氮化硅(Si3N4)介质层。在本发明的一个特殊的实施例中，栅介质层212是形成为厚度在5-
Figure A20068003552100091
之间的氮氧化硅膜片。在本发明另一实施例中，栅电介质层212是高K栅介质层，诸如金属氧化物介质，诸如(但不限于)氧化钽、氧化钛、二氧化铪、氧化锆和氧化铝。栅介质层212可为其它类型高K介质，诸如(但不限于)铅锆钛酸盐(lead zirconium titanate(PZT))。
[0016]晶体管10、20和30具有栅电极213，如图2所示。在某些实施例中，栅电极213与形成在各非平面型晶体管20、30侧壁的栅介质层212接触。在平面型实施例中，诸如晶体管10，栅电极213与顶面218上的栅介质层接触。栅电极213具有一对由距离(该距离限定了晶体管10、20和30的栅极长度(Lg))分开的横向相对的侧壁。在本发明的实施例中，平面型晶体管10和非平面型晶体管20、30的Lg在约20nm和约30nm之间。栅电极213具有等于由栅电极213控制的半导体沟道的载流宽度的有效宽度。在本发明的实施例中，非平面型器件的有效载流宽度大于平面型器件的有效宽度。在一特定实施例中，如图2所示，各侧壁226、227的栅耦合侧壁高度都大于顶面218的宽度。如此，晶体管20的有效栅电极宽度大于晶体管10的有效栅电极宽度。在另一实施例中，晶体管10的栅电极的有效宽度大于晶体管20的栅电极的有效宽度。在本发明的又一实施例中，栅电极在平面型器件和非平面型器件之间、多个平面型器件之间或者多个非平面型器件之间物理连接，即是连续的。
[0017]图2的栅电极213可用任何具有适当的功函数的合适栅电极材料形成。在本发明的实施例中，栅电极包括多晶硅。在另外实施例中，栅电极由金属构成，诸如钨、氮化钽、氮化钛或硅化钛、硅化镍、硅化钴。适当地，栅电极213不必一定是单一材料，而可以为薄膜的复合(诸如金属/多晶硅电极)叠层。
[0018]晶体管10、20和30，如图2所示，各具有源区216和漏区217。源区216和漏区217形成在有源区中栅电极213的两个对侧。源区216和漏区217形成为具有相同的导电型，诸如n型或p型，具体取决于晶体管是nMOS器件还是pMOS器件。在本发明的一实施例中，源区216和漏区217具有掺杂浓度1x1019-1x1021原子/cm3。源区216和漏区217可形成为单一浓度，或者它们能够包括不同浓度的子区域或者不同杂质分布的子区域，诸如尖端区(例如，源极或者漏极扩展区)。
[0019]如图2所示，晶体管10、20和30各具有沟道区，该沟道区在栅电极213之下、在位于源区216和漏区217之间的有源区中。晶体管10、20和30的沟道区可独立地掺杂到适用于特殊器件几何结构、栅堆叠和性能要求的杂质水平。沟道区掺杂时，一般将源区216和漏区217掺杂成相对的导电型。例如，nMOS器件205具有n导电型的源区和漏区，而沟道区掺杂成p导电型。在本发明的某些实施例中，非平面型器件20、30的沟道区是本征的即未掺杂的，而平面型器件的沟道区则是掺杂的。在本发明的实施例中，晶体管10、20和30沟道区都是掺杂的。沟道区掺杂时，能够掺杂到导电性为1x1016-1x1019原子/cm3的程度。
[0020]根据本发明实施例(如图2中所示的)在体衬底上制作CMOS器件的一种方法，在图3A-3G中举例说明。在一特定实施例中，从″块状″单晶硅衬底201开始制作。在本发明的某些实施例中，衬底201是具有掺杂外延区的硅半导体，该掺杂质外延区具有杂质浓度在1x1016-1x1019原子/cm3之间的p导电型或者n导电型。在本发明的另一实施例中，衬底201是具有非掺杂即本征外延硅区的硅半导体。在其它实施例中，体衬底201是任何其它已知的半导体材料，诸如砷化镓(GaAs)、锑化铟(InSb)、锑化镓(GaSb)、磷化镓(GaP)、磷化铟(InP)或碳纳米管(CNT)。
[0021]掩模用于限定晶体管的有源区。掩模可为任何适用于限定半导体衬底的公知的材料。如图3A所示，在本发明的实施例中，掩模310由光刻限定并经蚀刻的介质材料形成。在另一实施例中，掩模310本身是可光刻限定的(photo-definable)材料。在一特定实施例中，如图3A所示，掩模层310可为材料的复合叠层，诸如氧化物/氮化物叠层。如果掩模层310是介质材料，则可用公知的工艺方法，诸如化学汽相淀积(CVD)、低压化学汽相淀积(LPCVD)、等离增强化学汽相淀积(PECVD)或均匀旋涂工艺来淀积掩模材料，同时可用公知的光刻和蚀刻工艺来限定掩模。在本发明的一实施例中，用最小的光刻尺寸来限定掩模310的宽度。在另一实施例中，掩模310的最小宽度是亚光刻的，它由公知的工艺方法形成，诸如干显影(dry develop)工艺、氧化/剥离工艺或基于隔层的(spacer-based)工艺。在本发明的一特定实施例中，掩模310的宽度小于30纳米，更具体地说，小于20纳米。
[0022]如图3B所示，掩模层310一旦界定，就用公知的方法蚀刻体衬底201上的半导体的一部分，以在衬底上与掩模310对齐地形成凹部或槽320。绝缘蚀刻限定的有源区具有足以将各元件相互绝缘的深度，并形成足够高度的栅耦合侧壁，以达到非平面型晶体管最大的理想沟道宽度。在本发明的一特定实施例中，槽320蚀刻成深度等于非平面型晶体管最大理想沟道宽度加上约
Figure A20068003552100111
至约以容纳介质绝缘区。在又一实施例中，槽320蚀刻成深度为约
Figure A20068003552100121
至之间。
[0023]如图3C所示，然后用介质将槽320填充，以在衬底201上形成浅槽绝缘(STI)区210。在本发明一实施例中，在槽320底部和侧壁上用公知的方法(诸如热氧化或热氮化)形成氧化物或氮化物衬垫。接着，通过例如高密度等离子(HDP)化学汽相淀积工序，在衬垫上以毯式淀积氧化物的方式填充槽320。淀积工序还将在掩模310顶面形成电介质层。然后，填充的介质层可通过化学、机械或电化学研磨工艺从掩模310顶部去除。持续研磨直到掩模310露出而形成绝缘区210，如图3C所示。在本发明的一特定实施例中，用一些公知的方法选择性也去除掩模310。在另一实施例中，如图3C所示，保留了掩模310的一部分。
[0024]如果需要，然后可为pMOS和nMOS晶体管选择性地形成阱区。阱区可通过用任何公知的工艺掺杂有源区使之具有所要求的杂质浓度来形成。在本发明的实施例中，使用公知的掩模和离子注入工艺，有源区204、224和244选择性地掺杂成带有浓度约为1x1016-1x1019原子/cm3之间的p导电型或n导电型。在一特定实施例中，阱区延伸到半导体的深处，比有源区的底面208、228和248深约
Figure A20068003552100123
如图3C所示。在本发明的实施例中，在选择性的阱区注入和掩模剥离之后，通过公知的净化方法(诸如用HF)从有源区顶面218、238和258去除掩模310或天然氧化物。在本发明的又一实施例中，用公知的工艺在顶面218、238和258生长或沉积牺牲氧化物。
[0025]然后可用掩模材料选择性地保护绝缘区，以能够选择性地限定非平面型器件。在一实施例中，如图3D所示，掩模330以类似于上述的方式(参考图3A)形成。掩模330或者是可光刻限定的材料或者是公知的″硬″掩模材料，该掩模材料通常由光刻术和蚀刻工艺图案化(patterned)。在图3D所示的实施例中，掩模330是可光刻限定的材料光刻胶(photoresist)。如图3D所示，掩模330用于保护与平面型器件10的有源区204和有源区224邻接的绝缘区210。如果需要，可采用另外的掩模层，以选择性地保护不同的其它绝缘区。
[0026]接着，未由掩模保护的绝缘区被蚀刻而凹陷，以使得非平面型晶体的有源区管侧壁露出。如图3E所示，未由掩模330保护的绝缘区210被蚀刻，而半导体有源区224没有被显著蚀刻，使得半导体侧壁226和227的至少一部分露出。在半导体有源区为硅的实施例中，绝缘区210可用包括氟离子的蚀刻剂(诸如HF)来形成凹陷。在一些实施例，绝缘区210用公知的各向异性蚀刻工艺来形成凹陷，诸如使用气体蚀刻剂(诸如但不限于C2F6)的等离子工艺或RIE工艺。在又一实施例中，可在各向异性蚀刻工艺后进行各向同性(isotropic)蚀刻，诸如公知的使用气体(诸如NF3)的干法蚀刻工艺，或者公知的湿法蚀刻工艺(诸如HF)，以完全将绝缘介质从半导体有源区侧壁的至少一部分去除。在一些实施例中，仅有未保护的绝缘区部分在凹陷蚀刻期间被去除。在一特定实施例(未图示)中，凹陷蚀刻选择性地作用于绝缘填充材料上的绝缘衬垫材料，使得沿着衬垫区而直接邻接于有源区的绝缘凹陷蚀刻深于绝缘填充区。以这种方式，凹陷蚀刻的宽度可用衬垫宽度紧密控制，以能够实现高的晶体管组装密度。
[0027]在非选择性均即毯式凹陷蚀刻之后，接着还使绝缘区选择性地凹陷一定的量，使该凹陷量达到设计的非平面型晶体管沟道宽度所要求的最终栅耦合侧壁高度。晶体管的最终栅耦合侧壁高度由相邻绝缘区凹陷的累积量即深度决定。绝缘凹陷深度受限于器件的绝缘要求和适度的纵横比(aspectratios)。例如，如果绝缘凹陷产生太大的纵横比，后续加工就会无意中造成隔层的后果(spacer artifacts)。在本发明的一特定实施例中，使绝缘区的一部分凹陷，其最终绝缘厚度为约至约
Figure A20068003552100132
之间。在其它实施例中，最终绝缘厚度显著大于约
Figure A20068003552100133
在本发明的一实施例中，绝缘区210凹陷大约与半导体有源区224顶面238的宽度相同的量。在其它实施例中，绝缘区210凹陷显著大于顶面238的宽度。
[0028]在本发明的实施例中，如图3F所示，掩模330用公知的方法去除，而第二掩模340以类似于前面参考图3D讨论的方式形成。掩模340保护有源区224，而围绕有源区244的绝缘区210如图3E所示被加工成凹陷。在本实施例中，相比于224，对于244能够达到不同的侧壁高度，因此，相比于非平面型晶体管20形成具有不同沟道宽度的非平面型晶体管30。应当理解，选择性地用掩模覆盖绝缘区的一部分和绝缘区的一定量的凹陷蚀刻的工序，可重复许多次，并用许多方法达到一系列的栅耦合侧壁高度，根据本发明对应于一系列的非平面型晶体管沟道宽度。
[0029]一旦选择性的绝缘凹陷蚀刻完成，用公知的工艺方法去除所有绝缘掩模。如果需要，可在所有的有源区执行最终清理，诸如HF清理，使所有绝缘区进一步凹陷。在本发明的一特定实施例中，另外进行牺牲氧化和毯式氧化蚀刻或清理，以提高半导体表面质量，再进一步经由角部倒园(cornerrounding)、特征收缩(feature shrinking)等来定制有源区的形状。
[0030]然后，可根据非平面型器件(双栅、三栅等)的类型，在有源区上形成栅介质层。在本发明的三栅实施例中，如图3G所示，栅介质层212形成在各源区204、224和224的顶面上，以及在或邻接于非平面型器件露出的侧壁226、227和246、247上形成。在某些实施例中，诸如双栅实施例，栅介质不是形成在非平面型有源区的顶面上。栅介质可为沉积的介质或生长的介质。在本发明的实施例中，栅介质层212是以干/湿法氧化工艺生长的氧化硅介质膜。在本发明的一实施例中，栅介质膜212是沉积的高K金属氧化物介质，诸如五氧化钽(tantalum pentaoxide)、氧化钛、二氧化铪、氧化锆和氧化铝或另一高K介质，诸如钛酸钡锶(barium strontium titanate(BST))。高K膜可用已知的工艺方法(诸如化学汽相沉淀(CVD)和原子层沉淀(ALD))形成。
[0031]然后在各有源区上形成栅电极。在本发明的实施例中，如图3G所示，栅电极213在顶面218、238、258的上方形成，并沿着侧壁226、227和246、247形成在栅介质层212上或者与之相邻。栅电极能够形成为厚度在200至
Figure A20068003552100141
之间。在特定实施例中，栅电极材料的厚度由绝缘区凹陷蚀刻的深度限定，因为栅电极材料往往会沿着凹陷蚀刻产生的外形(topography)而形成导电的隔层(spacer)。对于这样的实施例，栅电极材料的过度蚀刻能够防止因绝缘凹部深度小于栅电极材料的厚度而造成这样的隔层后果(spacer artifacts)。在一实施例中，栅电极具有至少三倍于栅耦合侧壁高度(前面定义为有源区侧壁的露出部分)的厚度。在本发明的一实施例中，栅电极包括多晶硅。在本发明的一些实施例中，栅极材料是金属，诸如(但不限于)钨、氧化钽、氮化钛或硅化钛、硅化镍、或硅化钴。在又一些实施例中，电极由多晶硅(poly-silicon)和金属的复合物形成。在本发明的一实施例中，栅电极213用公知的工艺方法形成，诸如在衬底上毯式地沉积栅电极材料，然后将栅电极材料图案化。在本发明的其它实施例中，栅电极使用“取代栅”(″replacement gate″)方法形成。在这些实施例中，栅电极使用类似于通常在波纹金属化(damascene metallization)工艺中使用的填充和研磨方法，通过该法可将凹陷的绝缘区用栅电极材料完全地填充。
[0032]在本发明的一实施例中，晶体管10、20和30的源区216和漏区217形成在处于栅电极213两侧的有源区中，如图3G所示。对于pMOS晶体管，有源区掺杂成p导电型，掺杂浓度在1x1019-1x1021原子/cm3之间。对于nMOS晶体管，有源区掺杂n导电型的离子，浓度在1x1019-1x1021原子/cm3之间。至此，本发明的CMOS晶体管基本上完成，剩余的仅是器件的相互连接。
[0033]尽管本发明已经就结构特征和/或方法作用作了描述，应该理解，由所附的权利要求书限定的本发明不必一定限于所描述的具体特征或作用。倒不如说，这些具体特征和作用作为要求保护的本发明的特别适合的实现方式而被公开。

Claims (20)

1.一种器件，包括：
在块状半导体衬底上形成的平面型晶体管和非平面型晶体管。
2.根据权利要求1所述的器件，其中，所述平面型晶体管在微处理器核中，而所述非平面型晶体管在微处理器SRAM区中。
3.根据权利要求1所述的器件，其中，所述平面型晶体管具有小于所述非平面型晶体管的沟道宽度。
4.一种半导体器件，包括：
具有基本上由块状半导体衬底上的相邻绝缘区覆盖的侧壁的第一有源区；
具有在所述块状半导体衬底上的相邻绝缘区的顶面上延伸的侧壁的第二有源区；
在所述第一有源区的顶面上的第一栅绝缘层和与所述第二有源区的所述侧壁的至少一部分相邻的第二栅绝缘层；
在所述第一栅绝缘层上的第一栅电极和与所述第二栅绝缘层相邻的第二栅电极；以及
在所述第一栅电极的相对的两侧的第一对源/漏区和在所述第二栅电极的相对的两侧的第二对源/漏区。
5.根据权利要求4所述的器件，其中，所述第二栅绝缘层在所述第二有源区的顶面上，而所述第二栅电极在所述第二栅绝缘层上。
6.根据权利要求4所述的器件，其中，所述第一栅电极和所述第二栅电极物理地连接。
7.一种器件，包括：在块状半导体衬底上形成的、具有第一沟道宽度的第一多栅晶体管和具有第二沟道宽度的第二多栅晶体管，其中，所述第一沟道宽度不同于所述第二沟道宽度。
8.根据权利要求7所述的器件，其中，所述第一多栅晶体管具有第一栅耦合侧壁高度，而所述第二多栅晶体管具有不同于所述第一栅耦合侧壁高度的第二栅耦合侧壁高度。
9.根据权利要求7所述的器件，还包括在所述块状半导体衬底上形成的单栅晶体管。
10.一种形成平面型和非平面型晶体管的方法，包括如下步骤：
形成具有与块状半导体衬底上的第一绝缘区相邻的侧壁的第一有源区；
形成具有与所述块状半导体衬底上的第二绝缘区相邻的侧壁的第二有源区；
通过使所述第二绝缘区的顶面凹陷，露出所述第二有源区的所述侧壁的至少一部分；
在所述第一有源区的所述顶面上形成第一栅绝缘层；
形成与所述第二有源区的所述侧壁的至少一部分相邻的第二栅绝缘层；
在所述第一栅绝缘层上形成第一栅电极；
形成与所述第二栅绝缘层相邻的第二栅电极；以及
在所述第一有源区和所述第二有源区中，在所述第一栅电极的相对的两侧形成第一对源/漏区，并在所述第二栅电极的相对的两侧形成第二对源/漏区。
11.根据权利要求10所述的方法，其中，用包含氟化物离子的蚀刻剂使所述第二绝缘区的所述顶面凹陷。
12.根据权利要求10所述的方法，其中，用各向异性蚀刻使所述第二绝缘区的所述顶面凹陷。
13.根据权利要求10所述的方法，其中，所述绝缘区的衬垫区以大于所述绝缘区的相邻填充区的量凹陷。
14.根据权利要求10所述的方法，其中，还包括以光刻方式限定要被凹陷的所述第二绝缘区。
15.根据权利要求10所述的方法，其中，在使所述第二绝缘区的所述顶面凹陷前，在所述第一和所述第二有源区的顶面上形成牺牲氧化层。
16.根据权利要求10所述的方法，其中，形成所述第一和所述第二栅电极的步骤包含取代栅工艺。
17.根据权利要求10所述的方法，其中，限定所述第一和所述第二栅电极的步骤包含蚀刻所述栅电极材料，以从所述第二有源区的所述侧壁上基本去除所述栅电极。
18.一种形成非平面型晶体管的方法，包括如下步骤：
形成具有与块状半导体衬底上的第一绝缘区相邻的侧壁的第一有源区；
形成具有与所述块状半导体衬底上的第二绝缘区相邻的侧壁的第二有源区；
使所述第一绝缘区的顶面以第一量凹陷，以露出所述第一有源区的所述侧壁的至少一部分；
使所述第二绝缘区的顶面以第二量凹陷，以露出所述第二有源区的所述侧壁的至少一部分，凹陷的所述第二量不同于凹陷的所述第一量；
形成与所述第一有源区的所述侧壁的至少一部分相邻的第一栅绝缘层，并形成与所述第二有源区的所述侧壁的至少一部分相邻的第二栅绝缘层；
形成与所述第一栅绝缘层相邻的第一栅电极，并形成与所述第二栅绝缘层相邻的第二栅电极；以及
在所述第一栅电极的相对的两侧形成第一对源/漏区，并在所述第二栅电极的相对的两侧形成第二对源/漏区。
19.根据权利要求18所述的方法，还包括如下步骤：
在所述第一有源区的顶面上形成第一栅绝缘层和第一栅电极；以及
在所述第二有源区的顶面上形成第二栅绝缘层和第二栅电极。
20.根据权利要求18所述的方法，还包括如下步骤：
在形成所述第一栅绝缘层和所述第二栅绝缘层前，毯式地蚀刻牺牲氧化层。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102449769A (zh) * 2009-06-03 2012-05-09 高通股份有限公司 制造电子装置的设备和方法
CN103137621A (zh) * 2011-11-25 2013-06-05 三星电子株式会社 半导体器件及其制造方法
CN104011842A (zh) * 2011-12-31 2014-08-27 英特尔公司 用于高鳍状物的硬掩模蚀刻停止层
US9012284B2 (en) 2011-12-23 2015-04-21 Intel Corporation Nanowire transistor devices and forming techniques
CN109545802A (zh) * 2018-12-14 2019-03-29 上海微阱电子科技有限公司 一种绝缘体上半导体器件结构和形成方法

Families Citing this family (110)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7268058B2 (en) * 2004-01-16 2007-09-11 Intel Corporation Tri-gate transistors and methods to fabricate same
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US7332439B2 (en) * 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
KR100618900B1 (ko) * 2005-06-13 2006-09-01 삼성전자주식회사 다중 채널을 갖는 모스 전계효과 트랜지스터의 제조방법 및그에 따라 제조된 다중 채널을 갖는 모스 전계효과트랜지스터
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) * 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7364997B2 (en) * 2005-07-07 2008-04-29 Micron Technology, Inc. Methods of forming integrated circuitry and methods of forming local interconnects
KR100641944B1 (ko) * 2005-07-21 2006-11-02 주식회사 하이닉스반도체 반도체소자의 트랜지스터 및 그 형성방법
US20070090416A1 (en) 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
WO2007063990A1 (ja) * 2005-12-02 2007-06-07 Nec Corporation 半導体装置およびその製造方法
US7512017B2 (en) * 2005-12-21 2009-03-31 Intel Corporation Integration of planar and tri-gate devices on the same substrate
US7301210B2 (en) * 2006-01-12 2007-11-27 International Business Machines Corporation Method and structure to process thick and thin fins and variable fin to fin spacing
JP4490927B2 (ja) * 2006-01-24 2010-06-30 株式会社東芝 半導体装置
WO2007115954A1 (en) * 2006-04-07 2007-10-18 Koninklijke Philips Electronics N.V. Co-integration of multi-gate fet with other fet devices in cmos technology
KR100734088B1 (ko) * 2006-05-30 2007-07-02 주식회사 하이닉스반도체 트랜지스터의 제조방법
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
US8368144B2 (en) * 2006-12-18 2013-02-05 Infineon Technologies Ag Isolated multigate FET circuit blocks with different ground potentials
US20080157225A1 (en) * 2006-12-29 2008-07-03 Suman Datta SRAM and logic transistors with variable height multi-gate transistor architecture
US8017463B2 (en) * 2006-12-29 2011-09-13 Intel Corporation Expitaxial fabrication of fins for FinFET devices
US7692275B2 (en) 2007-02-26 2010-04-06 International Business Machines Corporation Structure and method for device-specific fill for improved anneal uniformity
US7745909B2 (en) 2007-02-26 2010-06-29 International Business Machines Corporation Localized temperature control during rapid thermal anneal
US7759773B2 (en) 2007-02-26 2010-07-20 International Business Machines Corporation Semiconductor wafer structure with balanced reflectance and absorption characteristics for rapid thermal anneal uniformity
US7679166B2 (en) 2007-02-26 2010-03-16 International Business Machines Corporation Localized temperature control during rapid thermal anneal
US7821061B2 (en) 2007-03-29 2010-10-26 Intel Corporation Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications
US7453125B1 (en) * 2007-04-24 2008-11-18 Infineon Technologies Ag Double mesh finfet
US20080283910A1 (en) * 2007-05-15 2008-11-20 Qimonda Ag Integrated circuit and method of forming an integrated circuit
US20090057780A1 (en) * 2007-08-27 2009-03-05 International Business Machines Corporation Finfet structure including multiple semiconductor fin channel heights
JP2009054946A (ja) * 2007-08-29 2009-03-12 Seiko Instruments Inc 半導体装置とその製造方法
KR101263648B1 (ko) * 2007-08-31 2013-05-21 삼성전자주식회사 핀 전계 효과 트랜지스터 및 그 제조 방법.
US8211786B2 (en) * 2008-02-28 2012-07-03 International Business Machines Corporation CMOS structure including non-planar hybrid orientation substrate with planar gate electrodes and method for fabrication
US8106459B2 (en) 2008-05-06 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs having dielectric punch-through stoppers
US7687862B2 (en) * 2008-05-13 2010-03-30 Infineon Technologies Ag Semiconductor devices with active regions of different heights
US7838355B2 (en) * 2008-06-04 2010-11-23 International Business Machines Corporation Differential nitride pullback to create differential NFET to PFET divots for improved performance versus leakage
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
DE102008030864B4 (de) * 2008-06-30 2010-06-17 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement als Doppelgate- und Tri-Gatetransistor, die auf einem Vollsubstrat aufgebaut sind und Verfahren zur Herstellung des Transistors
US8063447B2 (en) * 2008-08-06 2011-11-22 Intel Corporation Multiple-gate transistors and processes of making same
DE102008059646B4 (de) * 2008-11-28 2010-12-30 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines Halbleiterbauelements als Mehr-Gatetransistor mit Stegen mit einer Länge, die durch die Gateelektrode definiert ist und Halbleiterbauelement
US9379011B2 (en) 2008-12-19 2016-06-28 Asm International N.V. Methods for depositing nickel films and for making nickel silicide and nickel germanide
US7927942B2 (en) 2008-12-19 2011-04-19 Asm International N.V. Selective silicide process
US8293616B2 (en) 2009-02-24 2012-10-23 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of fabrication of semiconductor devices with low capacitance
US8324036B2 (en) * 2009-11-09 2012-12-04 International Business Machines Corporation Device having and method for forming fins with multiple widths for an integrated circuit
US8138543B2 (en) 2009-11-18 2012-03-20 International Business Machines Corporation Hybrid FinFET/planar SOI FETs
US8941153B2 (en) * 2009-11-20 2015-01-27 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with different fin heights
FR2961951A1 (fr) * 2010-06-23 2011-12-30 Commissariat Energie Atomique Transistor a largeur de grille effective augmentee, dispositif semi-conducteur comportant un tel transistor et procede de realisation
US8659072B2 (en) * 2010-09-24 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Series FinFET implementation schemes
US8354319B2 (en) * 2010-10-15 2013-01-15 International Business Machines Corporation Integrated planar and multiple gate FETs
US8524546B2 (en) 2010-10-22 2013-09-03 International Business Machines Corporation Formation of multi-height MUGFET
US8524545B2 (en) 2010-10-22 2013-09-03 International Business Machines Corporation Simultaneous formation of FinFET and MUGFET
US8871617B2 (en) 2011-04-22 2014-10-28 Asm Ip Holding B.V. Deposition and reduction of mixed metal oxide thin films
US8685825B2 (en) * 2011-07-27 2014-04-01 Advanced Ion Beam Technology, Inc. Replacement source/drain finFET fabrication
US8871584B2 (en) 2011-07-27 2014-10-28 Advanced Ion Beam Technology, Inc. Replacement source/drain finFET fabrication
US9105660B2 (en) 2011-08-17 2015-08-11 United Microelectronics Corp. Fin-FET and method of forming the same
US8969154B2 (en) * 2011-08-23 2015-03-03 Micron Technology, Inc. Methods for fabricating semiconductor device structures and arrays of vertical transistor devices
US8691651B2 (en) * 2011-08-25 2014-04-08 United Microelectronics Corp. Method of forming non-planar FET
US9287385B2 (en) 2011-09-01 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-fin device and method of making same
US8563376B2 (en) 2011-12-16 2013-10-22 International Business Machines Corporation Hybrid CMOS nanowire mesh device and bulk CMOS device
US8722472B2 (en) 2011-12-16 2014-05-13 International Business Machines Corporation Hybrid CMOS nanowire mesh device and FINFET device
US8709888B2 (en) 2011-12-16 2014-04-29 International Business Machines Corporation Hybrid CMOS nanowire mesh device and PDSOI device
CN104137265B (zh) 2011-12-22 2017-11-17 英特尔公司 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法
US9224810B2 (en) 2011-12-23 2015-12-29 Intel Corporation CMOS nanowire structure
JP5816560B2 (ja) * 2012-01-10 2015-11-18 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8587068B2 (en) 2012-01-26 2013-11-19 International Business Machines Corporation SRAM with hybrid FinFET and planar transistors
US9530901B2 (en) * 2012-01-31 2016-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. Decoupling finFET capacitors
US9368596B2 (en) * 2012-06-14 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for a field effect transistor
WO2014018201A1 (en) * 2012-07-27 2014-01-30 Intel Corporation Nanowire transistor devices and forming techniques
US8796772B2 (en) * 2012-09-24 2014-08-05 Intel Corporation Precision resistor for non-planar semiconductor device architecture
KR101983633B1 (ko) 2012-11-30 2019-05-29 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US8759874B1 (en) 2012-11-30 2014-06-24 Stmicroelectronics, Inc. FinFET device with isolated channel
US8956942B2 (en) 2012-12-21 2015-02-17 Stmicroelectronics, Inc. Method of forming a fully substrate-isolated FinFET transistor
US9318367B2 (en) 2013-02-27 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET structure with different fin heights and method for forming the same
US9074295B2 (en) 2013-03-15 2015-07-07 Raytheon Company Methods of etching carbon nanotube sheet material for electrical circuit and thin film thermal structure applications
US9356023B2 (en) * 2013-03-30 2016-05-31 Intel Corporation Planar device on fin-based transistor architecture
US10438856B2 (en) 2013-04-03 2019-10-08 Stmicroelectronics, Inc. Methods and devices for enhancing mobility of charge carriers
US20150021698A1 (en) * 2013-07-18 2015-01-22 International Business Machines Corporation Intrinsic Channel Planar Field Effect Transistors Having Multiple Threshold Voltages
US9064989B2 (en) 2013-08-30 2015-06-23 Taiwan Semiconductor Manufacturing Company Limited Photo diode and method of forming the same
US9153694B2 (en) 2013-09-04 2015-10-06 Globalfoundries Inc. Methods of forming contact structures on finfet semiconductor devices and the resulting devices
DE102014220672A1 (de) 2013-10-22 2015-05-07 Semiconductor Energy Laboratory Co., Ltd. Halbleitervorrichtung
EP2866264A1 (en) 2013-10-22 2015-04-29 IMEC vzw Method for manufacturing a field effect transistor of a non-planar type
US9147683B2 (en) * 2014-02-18 2015-09-29 International Business Machines Corporation CMOS transistors including gate spacers of the same thickness
US9947772B2 (en) 2014-03-31 2018-04-17 Stmicroelectronics, Inc. SOI FinFET transistor with strained channel
JP6537341B2 (ja) * 2014-05-07 2019-07-03 株式会社半導体エネルギー研究所 半導体装置
US9425275B2 (en) * 2014-06-13 2016-08-23 Samsung Electronics Co., Ltd. Integrated circuit chips having field effect transistors with different gate designs
CN106463533B (zh) 2014-06-20 2021-09-28 英特尔公司 高电压晶体管和低电压非平面晶体管的单片集成
US9502518B2 (en) 2014-06-23 2016-11-22 Stmicroelectronics, Inc. Multi-channel gate-all-around FET
US9362405B1 (en) * 2014-12-04 2016-06-07 Globalfoundries Inc. Channel cladding last process flow for forming a channel region on a FinFET device
KR102307467B1 (ko) * 2015-03-20 2021-09-29 삼성전자주식회사 액티브 핀을 포함하는 반도체 장치
US9461110B1 (en) * 2015-04-30 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. FETs and methods of forming FETs
US9666493B2 (en) * 2015-06-24 2017-05-30 International Business Machines Corporation Semiconductor device structure with 110-PFET and 111-NFET curent flow direction
US9905467B2 (en) * 2015-09-04 2018-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof
US9607842B1 (en) 2015-10-02 2017-03-28 Asm Ip Holding B.V. Methods of forming metal silicides
US9899378B2 (en) 2015-12-14 2018-02-20 International Business Machines Corporation Simultaneously fabricating a high voltage transistor and a finFET
US9502407B1 (en) * 2015-12-16 2016-11-22 International Business Machines Corporation Integrating a planar field effect transistor (FET) with a vertical FET
EP3182461B1 (en) * 2015-12-16 2022-08-03 IMEC vzw Method for fabricating finfet technology with locally higher fin-to-fin pitch
US9601497B1 (en) * 2016-04-28 2017-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Static random access memory and method of manufacturing the same
US9916978B2 (en) 2016-06-02 2018-03-13 United Microelectronics Corporation Method for fabricating a Fin field effect transistor (FinFET)
US10566361B2 (en) * 2016-12-14 2020-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Wide channel gate structure and method of forming
US10541205B1 (en) * 2017-02-14 2020-01-21 Intel Corporation Manufacture of interconnects for integration of multiple integrated circuits
CN108933134B (zh) * 2017-05-24 2020-09-25 清华大学 半导体器件
US10483167B2 (en) * 2017-08-15 2019-11-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing dual FinFET device
WO2019132928A1 (en) * 2017-12-28 2019-07-04 Intel Corporation Group iii-nitride (iii-n) logic and rf devices and their methods of fabrication
US11610887B2 (en) * 2019-01-09 2023-03-21 Intel Corporation Side-by-side integration of III-n transistors and thin-film transistors
TWI723878B (zh) * 2020-01-30 2021-04-01 旺宏電子股份有限公司 多閘極電晶體及應用其之記憶體裝置
DE102020112203A1 (de) * 2020-03-13 2021-09-16 Taiwan Semiconductor Manufacturing Co. Ltd. Verfahren zum einbetten planarer fets mit finfets
CN114497034A (zh) 2020-10-26 2022-05-13 联华电子股份有限公司 半导体元件
CN114530447B (zh) * 2022-04-24 2022-10-25 合肥晶合集成电路股份有限公司 半导体结构及其制作方法

Family Cites Families (349)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4231149A (en) 1978-10-10 1980-11-04 Texas Instruments Incorporated Narrow band-gap semiconductor CCD imaging device and method of fabrication
GB2156149A (en) 1984-03-14 1985-10-02 Philips Electronic Associated Dielectrically-isolated integrated circuit manufacture
US4487652A (en) 1984-03-30 1984-12-11 Motorola, Inc. Slope etch of polyimide
US5514885A (en) 1986-10-09 1996-05-07 Myrick; James J. SOI methods and apparatus
US4818715A (en) 1987-07-09 1989-04-04 Industrial Technology Research Institute Method of fabricating a LDDFET with self-aligned silicide
US4907048A (en) 1987-11-23 1990-03-06 Xerox Corporation Double implanted LDD transistor self-aligned with gate
US4905063A (en) 1988-06-21 1990-02-27 American Telephone And Telegraph Company, At&T Bell Laboratories Floating gate memories
JPH0214578A (ja) 1988-07-01 1990-01-18 Fujitsu Ltd 半導体装置
KR910010043B1 (ko) 1988-07-28 1991-12-10 한국전기통신공사 스페이서를 이용한 미세선폭 형성방법
US4994873A (en) 1988-10-17 1991-02-19 Motorola, Inc. Local interconnect for stacked polysilicon device
US5346834A (en) 1988-11-21 1994-09-13 Hitachi, Ltd. Method for manufacturing a semiconductor device and a semiconductor memory device
US4906589A (en) 1989-02-06 1990-03-06 Industrial Technology Research Institute Inverse-T LDDFET with self-aligned silicide
US5328810A (en) 1990-05-07 1994-07-12 Micron Technology, Inc. Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process
KR930003790B1 (ko) 1990-07-02 1993-05-10 삼성전자 주식회사 반도체 장치의 캐패시터용 유전체
JP3061406B2 (ja) 1990-09-28 2000-07-10 株式会社東芝 半導体装置
JP3202223B2 (ja) 1990-11-27 2001-08-27 日本電気株式会社 トランジスタの製造方法
US5521859A (en) 1991-03-20 1996-05-28 Fujitsu Limited Semiconductor memory device having thin film transistor and method of producing the same
DE69213539T2 (de) 1991-04-26 1997-02-20 Canon Kk Halbleitervorrichtung mit verbessertem isoliertem Gate-Transistor
JPH05152293A (ja) 1991-04-30 1993-06-18 Sgs Thomson Microelectron Inc 段差付き壁相互接続体及びゲートの製造方法
US5346836A (en) 1991-06-06 1994-09-13 Micron Technology, Inc. Process for forming low resistance contacts between silicide areas and upper level polysilicon interconnects
US5292670A (en) 1991-06-10 1994-03-08 Texas Instruments Incorporated Sidewall doping technique for SOI transistors
US5179037A (en) 1991-12-24 1993-01-12 Texas Instruments Incorporated Integration of lateral and vertical quantum well transistors in the same epitaxial stack
US5391506A (en) 1992-01-31 1995-02-21 Kawasaki Steel Corporation Manufacturing method for semiconductor devices with source/drain formed in substrate projection.
JPH05243572A (ja) 1992-02-27 1993-09-21 Fujitsu Ltd 半導体装置
US5405454A (en) 1992-03-19 1995-04-11 Matsushita Electric Industrial Co., Ltd. Electrically insulated silicon structure and producing method therefor
JP2572003B2 (ja) 1992-03-30 1997-01-16 三星電子株式会社 三次元マルチチャンネル構造を有する薄膜トランジスタの製造方法
JPH0793441B2 (ja) 1992-04-24 1995-10-09 ヒュンダイ エレクトロニクス インダストリーズ カンパニー リミテッド 薄膜トランジスタ及びその製造方法
KR960002088B1 (ko) 1993-02-17 1996-02-10 삼성전자주식회사 에스오아이(SOI : silicon on insulator) 구조의 반도체 장치 제조방법
US5357119A (en) 1993-02-19 1994-10-18 Board Of Regents Of The University Of California Field effect devices having short period superlattice structures using Si and Ge
JPH06310547A (ja) 1993-02-25 1994-11-04 Mitsubishi Electric Corp 半導体装置及びその製造方法
EP0623963A1 (de) 1993-05-06 1994-11-09 Siemens Aktiengesellschaft MOSFET auf SOI-Substrat
US5739544A (en) 1993-05-26 1998-04-14 Matsushita Electric Industrial Co., Ltd. Quantization functional device utilizing a resonance tunneling effect and method for producing the same
GB2282736B (en) 1993-05-28 1996-12-11 Nec Corp Radio base station for a mobile communications system
US6730549B1 (en) 1993-06-25 2004-05-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for its preparation
JP3778581B2 (ja) 1993-07-05 2006-05-24 三菱電機株式会社 半導体装置およびその製造方法
US5398641A (en) 1993-07-27 1995-03-21 Texas Instruments Incorporated Method for p-type doping of semiconductor structures formed of group II and group VI elements
JP3460863B2 (ja) 1993-09-17 2003-10-27 三菱電機株式会社 半導体装置の製造方法
US5479033A (en) 1994-05-27 1995-12-26 Sandia Corporation Complementary junction heterostructure field-effect transistor
JP3361922B2 (ja) 1994-09-13 2003-01-07 株式会社東芝 半導体装置
JP3378414B2 (ja) 1994-09-14 2003-02-17 株式会社東芝 半導体装置
JPH08153880A (ja) 1994-09-29 1996-06-11 Toshiba Corp 半導体装置及びその製造方法
US5602049A (en) 1994-10-04 1997-02-11 United Microelectronics Corporation Method of fabricating a buried structure SRAM cell
JPH08125152A (ja) 1994-10-28 1996-05-17 Canon Inc 半導体装置、それを用いた相関演算装置、ａｄ変換器、ｄａ変換器、信号処理システム
JP3078720B2 (ja) 1994-11-02 2000-08-21 三菱電機株式会社 半導体装置およびその製造方法
GB2295488B (en) 1994-11-24 1996-11-20 Toshiba Cambridge Res Center Semiconductor device
US5716879A (en) 1994-12-15 1998-02-10 Goldstar Electron Company, Ltd. Method of making a thin film transistor
JPH08204191A (ja) 1995-01-20 1996-08-09 Sony Corp 電界効果トランジスタ及びその製造方法
US5665203A (en) 1995-04-28 1997-09-09 International Business Machines Corporation Silicon etching method
JP3303601B2 (ja) * 1995-05-19 2002-07-22 日産自動車株式会社 溝型半導体装置
KR0165398B1 (ko) 1995-05-26 1998-12-15 윤종용 버티칼 트랜지스터의 제조방법
US5814545A (en) 1995-10-02 1998-09-29 Motorola, Inc. Semiconductor device having a phosphorus doped PECVD film and a method of manufacture
US5658806A (en) 1995-10-26 1997-08-19 National Science Council Method for fabricating thin-film transistor with bottom-gate or dual-gate configuration
US5814895A (en) 1995-12-22 1998-09-29 Sony Corporation Static random access memory having transistor elements formed on side walls of a trench in a semiconductor substrate
KR100205442B1 (ko) 1995-12-26 1999-07-01 구본준 박막트랜지스터 및 그의 제조방법
US5595919A (en) 1996-02-20 1997-01-21 Chartered Semiconductor Manufacturing Pte Ltd. Method of making self-aligned halo process for reducing junction capacitance
DE19607209A1 (de) 1996-02-26 1997-08-28 Gregor Kohlruss Reinigungsvorrichtung zum Reinigen von flächigen Gegenständen
EP0802483B1 (en) * 1996-04-18 2002-01-30 STMicroelectronics S.r.l. Semiconductor memory device with row redundancy
JPH09293793A (ja) 1996-04-26 1997-11-11 Mitsubishi Electric Corp 薄膜トランジスタを有する半導体装置およびその製造方法
US5793088A (en) 1996-06-18 1998-08-11 Integrated Device Technology, Inc. Structure for controlling threshold voltage of MOSFET
JP3710880B2 (ja) * 1996-06-28 2005-10-26 株式会社東芝 不揮発性半導体記憶装置
TW548686B (en) 1996-07-11 2003-08-21 Semiconductor Energy Lab CMOS semiconductor device and apparatus using the same
US5817560A (en) 1996-09-12 1998-10-06 Advanced Micro Devices, Inc. Ultra short trench transistors and process for making same
US6399970B2 (en) 1996-09-17 2002-06-04 Matsushita Electric Industrial Co., Ltd. FET having a Si/SiGeC heterojunction channel
US6063675A (en) 1996-10-28 2000-05-16 Texas Instruments Incorporated Method of forming a MOSFET using a disposable gate with a sidewall dielectric
US6063677A (en) 1996-10-28 2000-05-16 Texas Instruments Incorporated Method of forming a MOSFET using a disposable gate and raised source and drain
US6163053A (en) 1996-11-06 2000-12-19 Ricoh Company, Ltd. Semiconductor device having opposite-polarity region under channel
US5827769A (en) 1996-11-20 1998-10-27 Intel Corporation Method for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrode
JPH10150185A (ja) * 1996-11-20 1998-06-02 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5773331A (en) 1996-12-17 1998-06-30 International Business Machines Corporation Method for making single and double gate field effect transistors with sidewall source-drain contacts
US5908313A (en) * 1996-12-31 1999-06-01 Intel Corporation Method of forming a transistor
JP4086926B2 (ja) * 1997-01-29 2008-05-14 富士通株式会社 半導体装置及びその製造方法
JPH118390A (ja) 1997-06-18 1999-01-12 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6251763B1 (en) * 1997-06-30 2001-06-26 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing same
US6054355A (en) * 1997-06-30 2000-04-25 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device which includes forming a dummy gate
JPH1140811A (ja) 1997-07-22 1999-02-12 Hitachi Ltd 半導体装置およびその製造方法
US5952701A (en) 1997-08-18 1999-09-14 National Semiconductor Corporation Design and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor value
US5776821A (en) 1997-08-22 1998-07-07 Vlsi Technology, Inc. Method for forming a reduced width gate electrode
US6066869A (en) 1997-10-06 2000-05-23 Micron Technology, Inc. Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor
US5976767A (en) 1997-10-09 1999-11-02 Micron Technology, Inc. Ammonium hydroxide etch of photoresist masked silicon
US6120846A (en) * 1997-12-23 2000-09-19 Advanced Technology Materials, Inc. Method for the selective deposition of bismuth based ferroelectric thin films by chemical vapor deposition
US5888309A (en) 1997-12-29 1999-03-30 Taiwan Semiconductor Manufacturing Company, Ltd. Lateral etch inhibited multiple for forming a via through a microelectronics layer susceptible to etching within a fluorine containing plasma followed by an oxygen containing plasma
US6117741A (en) 1998-01-09 2000-09-12 Texas Instruments Incorporated Method of forming a transistor having an improved sidewall gate structure
US6294416B1 (en) 1998-01-23 2001-09-25 Texas Instruments-Acer Incorporated Method of fabricating CMOS transistors with self-aligned planarization twin-well by using fewer mask counts
US6097065A (en) 1998-03-30 2000-08-01 Micron Technology, Inc. Circuits and methods for dual-gated transistors
US6307235B1 (en) 1998-03-30 2001-10-23 Micron Technology, Inc. Another technique for gated lateral bipolar transistors
US6087208A (en) 1998-03-31 2000-07-11 Advanced Micro Devices, Inc. Method for increasing gate capacitance by using both high and low dielectric gate material
US6215190B1 (en) 1998-05-12 2001-04-10 International Business Machines Corporation Borderless contact to diffusion with respect to gate conductor and methods for fabricating
US6232641B1 (en) 1998-05-29 2001-05-15 Kabushiki Kaisha Toshiba Semiconductor apparatus having elevated source and drain structure and manufacturing method therefor
US6114201A (en) 1998-06-01 2000-09-05 Texas Instruments-Acer Incorporated Method of manufacturing a multiple fin-shaped capacitor for high density DRAMs
US6317444B1 (en) 1998-06-12 2001-11-13 Agere System Optoelectronics Guardian Corp. Optical device including carbon-doped contact layers
US6165880A (en) 1998-06-15 2000-12-26 Taiwan Semiconductor Manufacturing Company Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits
US6130123A (en) 1998-06-30 2000-10-10 Intel Corporation Method for making a complementary metal gate electrode technology
JP2000037842A (ja) 1998-07-27 2000-02-08 Dainippon Printing Co Ltd 電磁波吸収化粧材
US6696366B1 (en) 1998-08-17 2004-02-24 Lam Research Corporation Technique for etching a low capacitance dielectric layer
JP2000156502A (ja) 1998-09-21 2000-06-06 Texas Instr Inc <Ti> 集積回路及び方法
US6153485A (en) 1998-11-09 2000-11-28 Chartered Semiconductor Manufacturing Ltd. Salicide formation on narrow poly lines by pulling back of spacer
US6362111B1 (en) 1998-12-09 2002-03-26 Texas Instruments Incorporated Tunable gate linewidth reduction process
TW449919B (en) 1998-12-18 2001-08-11 Koninkl Philips Electronics Nv A method of manufacturing a semiconductor device
TW406312B (en) 1998-12-18 2000-09-21 United Microelectronics Corp The method of etching doped poly-silicon
US6380558B1 (en) 1998-12-29 2002-04-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
US6150222A (en) 1999-01-07 2000-11-21 Advanced Micro Devices, Inc. Method of making a high performance transistor with elevated spacer formation and self-aligned channel regions
FR2788629B1 (fr) 1999-01-15 2003-06-20 Commissariat Energie Atomique Transistor mis et procede de fabrication d'un tel transistor sur un substrat semiconducteur
US6174820B1 (en) 1999-02-16 2001-01-16 Sandia Corporation Use of silicon oxynitride as a sacrificial material for microelectromechanical devices
JP2000243854A (ja) 1999-02-22 2000-09-08 Toshiba Corp 半導体装置及びその製造方法
US6093621A (en) 1999-04-05 2000-07-25 Vanguard International Semiconductor Corp. Method of forming shallow trench isolation
US7045468B2 (en) 1999-04-09 2006-05-16 Intel Corporation Isolated junction structure and method of manufacture
US6459123B1 (en) 1999-04-30 2002-10-01 Infineon Technologies Richmond, Lp Double gated transistor
DE60001601T2 (de) 1999-06-18 2003-12-18 Lucent Technologies Inc Fertigungsverfahren zur Herstellung eines CMOS integrieten Schaltkreises mit vertikalen Transistoren
JP2001015704A (ja) 1999-06-29 2001-01-19 Hitachi Ltd 半導体集積回路
US6218309B1 (en) 1999-06-30 2001-04-17 Lam Research Corporation Method of achieving top rounding and uniform etch depths while etching shallow trench isolation features
US6501131B1 (en) 1999-07-22 2002-12-31 International Business Machines Corporation Transistors having independently adjustable parameters
TW432594B (en) 1999-07-31 2001-05-01 Taiwan Semiconductor Mfg Manufacturing method for shallow trench isolation
US6259135B1 (en) * 1999-09-24 2001-07-10 International Business Machines Corporation MOS transistors structure for reducing the size of pitch limited circuits
FR2799305B1 (fr) 1999-10-05 2004-06-18 St Microelectronics Sa Procede de fabrication d'un dispositif semi-conducteur a grille enveloppante et dispositif obtenu
EP1091413A3 (en) 1999-10-06 2005-01-12 Lsi Logic Corporation Fully-depleted, fully-inverted, short-length and vertical channel, dual-gate, cmos fet
US6541829B2 (en) 1999-12-03 2003-04-01 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US6252284B1 (en) 1999-12-09 2001-06-26 International Business Machines Corporation Planarized silicon fin device
KR100311049B1 (ko) 1999-12-13 2001-10-12 윤종용 불휘발성 반도체 메모리장치 및 그의 제조방법
US6303479B1 (en) 1999-12-16 2001-10-16 Spinnaker Semiconductor, Inc. Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts
JP4923318B2 (ja) 1999-12-17 2012-04-25 ソニー株式会社 不揮発性半導体記憶装置およびその動作方法
JP4194237B2 (ja) * 1999-12-28 2008-12-10 株式会社リコー 電界効果トランジスタを用いた電圧発生回路及び基準電圧源回路
JP3846706B2 (ja) 2000-02-23 2006-11-15 信越半導体株式会社 ウエーハ外周面取部の研磨方法及び研磨装置
US6483156B1 (en) 2000-03-16 2002-11-19 International Business Machines Corporation Double planar gated SOI MOSFET structure
FR2806832B1 (fr) 2000-03-22 2002-10-25 Commissariat Energie Atomique Transistor mos a source et drain metalliques, et procede de fabrication d'un tel transistor
TW466606B (en) * 2000-04-20 2001-12-01 United Microelectronics Corp Manufacturing method for dual metal gate electrode
JP2001338987A (ja) * 2000-05-26 2001-12-07 Nec Microsystems Ltd Ｍｏｓトランジスタのシャロートレンチ分離領域の形成方法
US6526996B1 (en) 2000-06-12 2003-03-04 Promos Technologies, Inc. Dry clean method instead of traditional wet clean after metal etch
US6391782B1 (en) 2000-06-20 2002-05-21 Advanced Micro Devices, Inc. Process for forming multiple active lines and gate-all-around MOSFET
KR100545706B1 (ko) 2000-06-28 2006-01-24 주식회사 하이닉스반도체 반도체 소자 제조방법
JP4112358B2 (ja) 2000-07-04 2008-07-02 インフィネオン テクノロジーズ アクチエンゲゼルシャフト 電界効果トランジスタ
US20020011612A1 (en) 2000-07-31 2002-01-31 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP2002047034A (ja) 2000-07-31 2002-02-12 Shinetsu Quartz Prod Co Ltd プラズマを利用したプロセス装置用の石英ガラス治具
US6403981B1 (en) * 2000-08-07 2002-06-11 Advanced Micro Devices, Inc. Double gate transistor having a silicon/germanium channel region
KR100338778B1 (ko) 2000-08-21 2002-05-31 윤종용 선택적 실리사이드 공정을 이용한 모스 트랜지스터의제조방법
US6358800B1 (en) 2000-09-18 2002-03-19 Vanguard International Semiconductor Corporation Method of forming a MOSFET with a recessed-gate having a channel length beyond photolithography limit
US6387820B1 (en) 2000-09-19 2002-05-14 Advanced Micro Devices, Inc. BC13/AR chemistry for metal overetching on a high density plasma etcher
JP4044276B2 (ja) 2000-09-28 2008-02-06 株式会社東芝 半導体装置及びその製造方法
US6562665B1 (en) 2000-10-16 2003-05-13 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology
US7163864B1 (en) 2000-10-18 2007-01-16 International Business Machines Corporation Method of fabricating semiconductor side wall fin
US6413802B1 (en) 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6396108B1 (en) 2000-11-13 2002-05-28 Advanced Micro Devices, Inc. Self-aligned double gate silicon-on-insulator (SOI) device
US6472258B1 (en) 2000-11-13 2002-10-29 International Business Machines Corporation Double gate trench transistor
US6716684B1 (en) 2000-11-13 2004-04-06 Advanced Micro Devices, Inc. Method of making a self-aligned triple gate silicon-on-insulator device
JP2002198441A (ja) * 2000-11-16 2002-07-12 Hynix Semiconductor Inc 半導体素子のデュアル金属ゲート形成方法
US6552401B1 (en) 2000-11-27 2003-04-22 Micron Technology Use of gate electrode workfunction to improve DRAM refresh
US20020100942A1 (en) 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6921947B2 (en) * 2000-12-15 2005-07-26 Renesas Technology Corp. Semiconductor device having recessed isolation insulation film
US6413877B1 (en) 2000-12-22 2002-07-02 Lam Research Corporation Method of preventing damage to organo-silicate-glass materials during resist stripping
JP2002198368A (ja) 2000-12-26 2002-07-12 Nec Corp 半導体装置の製造方法
US6537901B2 (en) 2000-12-29 2003-03-25 Hynix Semiconductor Inc. Method of manufacturing a transistor in a semiconductor device
TW561530B (en) 2001-01-03 2003-11-11 Macronix Int Co Ltd Process for fabricating CMOS transistor of IC devices employing double spacers for preventing short-channel effect
US6359311B1 (en) 2001-01-17 2002-03-19 Taiwan Semiconductor Manufacturing Co., Ltd. Quasi-surrounding gate and a method of fabricating a silicon-on-insulator semiconductor device with the same
US6403434B1 (en) 2001-02-09 2002-06-11 Advanced Micro Devices, Inc. Process for manufacturing MOS transistors having elevated source and drain regions and a high-k gate dielectric
US6475890B1 (en) 2001-02-12 2002-11-05 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology
JP2002246310A (ja) 2001-02-14 2002-08-30 Sony Corp 半導体薄膜の形成方法及び半導体装置の製造方法、これらの方法の実施に使用する装置、並びに電気光学装置
US6475869B1 (en) 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
US6630388B2 (en) 2001-03-13 2003-10-07 National Institute Of Advanced Industrial Science And Technology Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same
TW582071B (en) 2001-03-20 2004-04-01 Macronix Int Co Ltd Method for etching metal in a semiconductor
JP2002298051A (ja) 2001-03-30 2002-10-11 Mizuho Bank Ltd ポイント交換サービス・システム
US6458662B1 (en) 2001-04-04 2002-10-01 Advanced Micro Devices, Inc. Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed
KR100414217B1 (ko) 2001-04-12 2004-01-07 삼성전자주식회사 게이트 올 어라운드형 트랜지스터를 가진 반도체 장치 및그 형성 방법
US6645861B2 (en) 2001-04-18 2003-11-11 International Business Machines Corporation Self-aligned silicide process for silicon sidewall source and drain contacts
US6787402B1 (en) 2001-04-27 2004-09-07 Advanced Micro Devices, Inc. Double-gate vertical MOSFET transistor and fabrication method
US6902947B2 (en) 2001-05-07 2005-06-07 Applied Materials, Inc. Integrated method for release and passivation of MEMS structures
SG112804A1 (en) 2001-05-10 2005-07-28 Inst Of Microelectronics Sloped trench etching process
KR100363332B1 (en) 2001-05-23 2002-12-05 Samsung Electronics Co Ltd Method for forming semiconductor device having gate all-around type transistor
US6635923B2 (en) 2001-05-24 2003-10-21 International Business Machines Corporation Damascene double-gate MOSFET with vertical channel regions
US6506692B2 (en) 2001-05-30 2003-01-14 Intel Corporation Method of making a semiconductor device using a silicon carbide hard mask
DE10131276B4 (de) * 2001-06-28 2007-08-02 Infineon Technologies Ag Feldeffekttransistor und Verfahren zu seiner Herstellung
US6737333B2 (en) 2001-07-03 2004-05-18 Texas Instruments Incorporated Semiconductor device isolation structure and method of forming
JP2003017508A (ja) 2001-07-05 2003-01-17 Nec Corp 電界効果トランジスタ
US6534807B2 (en) 2001-08-13 2003-03-18 International Business Machines Corporation Local interconnect junction on insulator (JOI) structure
US6501141B1 (en) 2001-08-13 2002-12-31 Taiwan Semiconductor Manufacturing Company, Ltd Self-aligned contact with improved isolation and method for forming
US6764965B2 (en) 2001-08-17 2004-07-20 United Microelectronics Corp. Method for improving the coating capability of low-k dielectric layer
JP2003100902A (ja) 2001-09-21 2003-04-04 Mitsubishi Electric Corp 半導体装置の製造方法
US6689650B2 (en) 2001-09-27 2004-02-10 International Business Machines Corporation Fin field effect transistor with self-aligned gate
US6492212B1 (en) 2001-10-05 2002-12-10 International Business Machines Corporation Variable threshold voltage double gated transistors and method of fabrication
US20030085194A1 (en) 2001-11-07 2003-05-08 Hopkins Dean A. Method for fabricating close spaced mirror arrays
US7385262B2 (en) 2001-11-27 2008-06-10 The Board Of Trustees Of The Leland Stanford Junior University Band-structure modulation of nano-structures in an electric field
US6967351B2 (en) * 2001-12-04 2005-11-22 International Business Machines Corporation Finfet SRAM cell using low mobility plane for cell stability and method for forming
US6657259B2 (en) 2001-12-04 2003-12-02 International Business Machines Corporation Multiple-plane FinFET CMOS
US6610576B2 (en) 2001-12-13 2003-08-26 International Business Machines Corporation Method for forming asymmetric dual gate transistor
US6555879B1 (en) * 2002-01-11 2003-04-29 Advanced Micro Devices, Inc. SOI device with metal source/drain and method of fabrication
US6722946B2 (en) 2002-01-17 2004-04-20 Nutool, Inc. Advanced chemical mechanical polishing system with smart endpoint detection
US6583469B1 (en) 2002-01-28 2003-06-24 International Business Machines Corporation Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same
KR100442089B1 (ko) 2002-01-29 2004-07-27 삼성전자주식회사 노치된 게이트 전극을 갖는 모스 트랜지스터의 제조방법
KR100458288B1 (ko) 2002-01-30 2004-11-26 한국과학기술원 이중-게이트 ＦｉｎＦＥＴ 소자 및 그 제조방법
DE10203998A1 (de) 2002-02-01 2003-08-21 Infineon Technologies Ag Verfahren zum Herstellen einer zackenförmigen Struktur, Verfahren zum Herstellen eines Transistors, Verfahren zum Herstellen eines Floating Gate-Transistors, Transistor, Floating Gate-Transistor und Speicher-Anordnung
US6784071B2 (en) 2003-01-31 2004-08-31 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement
US20030151077A1 (en) 2002-02-13 2003-08-14 Leo Mathew Method of forming a vertical double gate semiconductor device and structure thereof
JP3782021B2 (ja) 2002-02-22 2006-06-07 株式会社東芝 半導体装置、半導体装置の製造方法、半導体基板の製造方法
US6660598B2 (en) 2002-02-26 2003-12-09 International Business Machines Corporation Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region
JP4370104B2 (ja) 2002-03-05 2009-11-25 シャープ株式会社 半導体記憶装置
US6639827B2 (en) * 2002-03-12 2003-10-28 Intel Corporation Low standby power using shadow storage
US6635909B2 (en) 2002-03-19 2003-10-21 International Business Machines Corporation Strained fin FETs structure and method
US6605498B1 (en) * 2002-03-29 2003-08-12 Intel Corporation Semiconductor transistor having a backfilled channel material
FR2838238B1 (fr) 2002-04-08 2005-04-15 St Microelectronics Sa Dispositif semiconducteur a grille enveloppante encapsule dans un milieu isolant
US6762469B2 (en) 2002-04-19 2004-07-13 International Business Machines Corporation High performance CMOS device structure with mid-gap metal gate
US6713396B2 (en) 2002-04-29 2004-03-30 Hewlett-Packard Development Company, L.P. Method of fabricating high density sub-lithographic features on a substrate
US6537885B1 (en) 2002-05-09 2003-03-25 Infineon Technologies Ag Transistor and method of manufacturing a transistor having a shallow junction formation using a two step EPI layer
US6642090B1 (en) 2002-06-03 2003-11-04 International Business Machines Corporation Fin FET devices from bulk semiconductor and method for forming
US7074623B2 (en) 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US6680240B1 (en) 2002-06-25 2004-01-20 Advanced Micro Devices, Inc. Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide
US7105891B2 (en) 2002-07-15 2006-09-12 Texas Instruments Incorporated Gate structure and method
US6974729B2 (en) 2002-07-16 2005-12-13 Interuniversitair Microelektronica Centrum (Imec) Integrated semiconductor fin device and a method for manufacturing such device
US6705571B2 (en) * 2002-07-22 2004-03-16 Northrop Grumman Corporation System and method for loading stores on an aircraft
US6919238B2 (en) 2002-07-29 2005-07-19 Intel Corporation Silicon on insulator (SOI) transistor and methods of fabrication
US6921702B2 (en) 2002-07-30 2005-07-26 Micron Technology Inc. Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
US6984585B2 (en) 2002-08-12 2006-01-10 Applied Materials Inc Method for removal of residue from a magneto-resistive random access memory (MRAM) film stack using a sacrificial mask layer
US6833556B2 (en) 2002-08-12 2004-12-21 Acorn Technologies, Inc. Insulated gate field effect transistor having passivated schottky barriers to the channel
US6891234B1 (en) * 2004-01-07 2005-05-10 Acorn Technologies, Inc. Transistor with workfunction-induced charge layer
US7358121B2 (en) 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US7163851B2 (en) 2002-08-26 2007-01-16 International Business Machines Corporation Concurrent Fin-FET and thick-body device fabrication
JP5179692B2 (ja) 2002-08-30 2013-04-10 富士通セミコンダクター株式会社 半導体記憶装置及びその製造方法
US6770516B2 (en) 2002-09-05 2004-08-03 Taiwan Semiconductor Manufacturing Company Method of forming an N channel and P channel FINFET device on the same semiconductor substrate
US6794313B1 (en) 2002-09-20 2004-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Oxidation process to improve polysilicon sidewall roughness
JP3556651B2 (ja) 2002-09-27 2004-08-18 沖電気工業株式会社 半導体装置の製造方法
US6800910B2 (en) 2002-09-30 2004-10-05 Advanced Micro Devices, Inc. FinFET device incorporating strained silicon in the channel region
JP4294935B2 (ja) 2002-10-17 2009-07-15 株式会社ルネサステクノロジ 半導体装置
US6706571B1 (en) 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
US6833588B2 (en) 2002-10-22 2004-12-21 Advanced Micro Devices, Inc. Semiconductor device having a U-shaped gate structure
US6706581B1 (en) 2002-10-29 2004-03-16 Taiwan Semiconductor Manufacturing Company Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices
US6611029B1 (en) 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates
US6787439B2 (en) 2002-11-08 2004-09-07 Advanced Micro Devices, Inc. Method using planarizing gate material to improve gate critical dimension in semiconductor devices
US6709982B1 (en) 2002-11-26 2004-03-23 Advanced Micro Devices, Inc. Double spacer FinFET formation
US6855990B2 (en) 2002-11-26 2005-02-15 Taiwan Semiconductor Manufacturing Co., Ltd Strained-channel multiple-gate transistor
US6825506B2 (en) 2002-11-27 2004-11-30 Intel Corporation Field effect transistor and method of fabrication
US6821834B2 (en) 2002-12-04 2004-11-23 Yoshiyuki Ando Ion implantation methods and transistor cell layout for fin type transistors
KR100487922B1 (ko) * 2002-12-06 2005-05-06 주식회사 하이닉스반도체 반도체소자의 트랜지스터 및 그 형성방법
US6686231B1 (en) 2002-12-06 2004-02-03 Advanced Micro Devices, Inc. Damascene gate process with sacrificial oxide in semiconductor devices
US6645797B1 (en) 2002-12-06 2003-11-11 Advanced Micro Devices, Inc. Method for forming fins in a FinFET device using sacrificial carbon layer
US7214991B2 (en) 2002-12-06 2007-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. CMOS inverters configured using multiple-gate transistors
US7728360B2 (en) 2002-12-06 2010-06-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple-gate transistor structure
US6869868B2 (en) 2002-12-13 2005-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a MOSFET device with metal containing gate structures
US6794718B2 (en) 2002-12-19 2004-09-21 International Business Machines Corporation High mobility crystalline planes in double-gate CMOS technology
JP4418760B2 (ja) 2002-12-20 2010-02-24 インターナショナル・ビジネス・マシーンズ・コーポレーション フィン型ｆｅｔおよびｃｍｏｓデバイスのための一体化アンチヒューズ構造
US6780694B2 (en) * 2003-01-08 2004-08-24 International Business Machines Corporation MOS transistor
US6803631B2 (en) 2003-01-23 2004-10-12 Advanced Micro Devices, Inc. Strained channel finfet
US6762483B1 (en) 2003-01-23 2004-07-13 Advanced Micro Devices, Inc. Narrow fin FinFET
US7259425B2 (en) * 2003-01-23 2007-08-21 Advanced Micro Devices, Inc. Tri-gate and gate around MOSFET devices and methods for making same
US6885055B2 (en) 2003-02-04 2005-04-26 Lee Jong-Ho Double-gate FinFET device and fabricating method thereof
WO2004073044A2 (en) 2003-02-13 2004-08-26 Massachusetts Institute Of Technology Finfet device and method to make same
US6855606B2 (en) 2003-02-20 2005-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-rod devices
US7105894B2 (en) 2003-02-27 2006-09-12 Taiwan Semiconductor Manufacturing Co., Ltd. Contacts to semiconductor fin devices
US6787854B1 (en) 2003-03-12 2004-09-07 Advanced Micro Devices, Inc. Method for forming a fin in a finFET device
US6716690B1 (en) 2003-03-12 2004-04-06 Advanced Micro Devices, Inc. Uniformly doped source/drain junction in a double-gate MOSFET
US6800885B1 (en) 2003-03-12 2004-10-05 Advance Micro Devices, Inc. Asymmetrical double gate or all-around gate MOSFET devices and methods for making same
TW582099B (en) 2003-03-13 2004-04-01 Ind Tech Res Inst Method of adhering material layer on transparent substrate and method of forming single crystal silicon on transparent substrate
JP4563652B2 (ja) 2003-03-13 2010-10-13 シャープ株式会社 メモリ機能体および微粒子形成方法並びにメモリ素子、半導体装置および電子機器
US6844238B2 (en) 2003-03-26 2005-01-18 Taiwan Semiconductor Manufacturing Co., Ltd Multiple-gate transistors with improved gate control
US20040191980A1 (en) 2003-03-27 2004-09-30 Rafael Rios Multi-corner FET for better immunity from short channel effects
US6790733B1 (en) 2003-03-28 2004-09-14 International Business Machines Corporation Preserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer
US6764884B1 (en) 2003-04-03 2004-07-20 Advanced Micro Devices, Inc. Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device
US6902962B2 (en) 2003-04-04 2005-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Silicon-on-insulator chip with multiple crystal orientations
TWI231994B (en) 2003-04-04 2005-05-01 Univ Nat Taiwan Strained Si FinFET
US7442415B2 (en) 2003-04-11 2008-10-28 Sharp Laboratories Of America, Inc. Modulated temperature method of atomic layer deposition (ALD) of high dielectric constant films
JP2004319704A (ja) * 2003-04-15 2004-11-11 Seiko Instruments Inc 半導体装置
TW200506093A (en) 2003-04-21 2005-02-16 Aviza Tech Inc System and method for forming multi-component films
US20070108514A1 (en) * 2003-04-28 2007-05-17 Akira Inoue Semiconductor device and method of fabricating the same
US7074656B2 (en) 2003-04-29 2006-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Doping of semiconductor fin devices
JP3976703B2 (ja) 2003-04-30 2007-09-19 エルピーダメモリ株式会社 半導体装置の製造方法
US6867433B2 (en) 2003-04-30 2005-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
US6838322B2 (en) 2003-05-01 2005-01-04 Freescale Semiconductor, Inc. Method for forming a double-gated semiconductor device
US6909147B2 (en) 2003-05-05 2005-06-21 International Business Machines Corporation Multi-height FinFETS
US6765303B1 (en) 2003-05-06 2004-07-20 Advanced Micro Devices, Inc. FinFET-based SRAM cell
US7045401B2 (en) 2003-06-23 2006-05-16 Sharp Laboratories Of America, Inc. Strained silicon finFET device
US6911383B2 (en) 2003-06-26 2005-06-28 International Business Machines Corporation Hybrid planar and finFET CMOS devices
US20040262683A1 (en) 2003-06-27 2004-12-30 Bohr Mark T. PMOS transistor strain optimization with raised junction regions
US6909151B2 (en) 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US6960517B2 (en) 2003-06-30 2005-11-01 Intel Corporation N-gate transistor
US6716686B1 (en) 2003-07-08 2004-04-06 Advanced Micro Devices, Inc. Method for forming channels in a finfet device
US6921982B2 (en) 2003-07-21 2005-07-26 International Business Machines Corporation FET channel having a strained lattice structure along multiple surfaces
KR100487566B1 (ko) 2003-07-23 2005-05-03 삼성전자주식회사 핀 전계 효과 트랜지스터 및 그 형성 방법
KR100487567B1 (ko) 2003-07-24 2005-05-03 삼성전자주식회사 핀 전계효과 트랜지스터 형성 방법
EP1519420A2 (en) 2003-09-25 2005-03-30 Interuniversitaire Microelectronica Centrum vzw ( IMEC) Multiple gate semiconductor device and method for forming same
US7301206B2 (en) 2003-08-01 2007-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
US6835618B1 (en) 2003-08-05 2004-12-28 Advanced Micro Devices, Inc. Epitaxially grown fin for FinFET
US6787406B1 (en) 2003-08-12 2004-09-07 Advanced Micro Devices, Inc. Systems and methods for forming dense n-channel and p-channel fins using shadow implanting
US7172943B2 (en) 2003-08-13 2007-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-gate transistors formed on bulk substrates
KR100496891B1 (ko) 2003-08-14 2005-06-23 삼성전자주식회사 핀 전계효과 트랜지스터를 위한 실리콘 핀 및 그 제조 방법
US7355253B2 (en) 2003-08-22 2008-04-08 International Business Machines Corporation Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates
US6877728B2 (en) 2003-09-04 2005-04-12 Lakin Manufacturing Corporation Suspension assembly having multiple torsion members which cooperatively provide suspension to a wheel
JP4439358B2 (ja) * 2003-09-05 2010-03-24 株式会社東芝 電界効果トランジスタ及びその製造方法
US7170126B2 (en) * 2003-09-16 2007-01-30 International Business Machines Corporation Structure of vertical strained silicon devices
US6970373B2 (en) 2003-10-02 2005-11-29 Intel Corporation Method and apparatus for improving stability of a 6T CMOS SRAM cell
US7612416B2 (en) 2003-10-09 2009-11-03 Nec Corporation Semiconductor device having a conductive portion below an interlayer insulating film and method for producing the same
US20050139860A1 (en) 2003-10-22 2005-06-30 Snyder John P. Dynamic schottky barrier MOSFET device and method of manufacture
US6946377B2 (en) 2003-10-29 2005-09-20 Texas Instruments Incorporated Multiple-gate MOSFET device with lithography independent silicon body thickness and methods for fabricating the same
US7138320B2 (en) * 2003-10-31 2006-11-21 Advanced Micro Devices, Inc. Advanced technique for forming a transistor having raised drain and source regions
KR100515061B1 (ko) 2003-10-31 2005-09-14 삼성전자주식회사 핀 전계 효과 트랜지스터를 갖는 반도체 소자 및 그 형성방법
US6867460B1 (en) 2003-11-05 2005-03-15 International Business Machines Corporation FinFET SRAM cell with chevron FinFET logic
US6831310B1 (en) 2003-11-10 2004-12-14 Freescale Semiconductor, Inc. Integrated circuit having multiple memory types and method of formation
US6885072B1 (en) * 2003-11-18 2005-04-26 Applied Intellectual Properties Co., Ltd. Nonvolatile memory with undercut trapping structure
US7545001B2 (en) * 2003-11-25 2009-06-09 Taiwan Semiconductor Manufacturing Company Semiconductor device having high drive current and method of manufacture therefor
US7183137B2 (en) 2003-12-01 2007-02-27 Taiwan Semiconductor Manufacturing Company Method for dicing semiconductor wafers
US7075150B2 (en) 2003-12-02 2006-07-11 International Business Machines Corporation Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique
US7018551B2 (en) 2003-12-09 2006-03-28 International Business Machines Corporation Pull-back method of forming fins in FinFets
US7388258B2 (en) 2003-12-10 2008-06-17 International Business Machines Corporation Sectional field effect devices
US7662689B2 (en) 2003-12-23 2010-02-16 Intel Corporation Strained transistor integration for CMOS
US7223679B2 (en) 2003-12-24 2007-05-29 Intel Corporation Transistor gate electrode having conductor material layer
US7105390B2 (en) 2003-12-30 2006-09-12 Intel Corporation Nonplanar transistors with metal gate electrodes
US7078282B2 (en) * 2003-12-30 2006-07-18 Intel Corporation Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films
US7247578B2 (en) * 2003-12-30 2007-07-24 Intel Corporation Method of varying etch selectivities of a film
US7705345B2 (en) 2004-01-07 2010-04-27 International Business Machines Corporation High performance strained silicon FinFETs device and method for forming same
US7268058B2 (en) 2004-01-16 2007-09-11 Intel Corporation Tri-gate transistors and methods to fabricate same
US7385247B2 (en) 2004-01-17 2008-06-10 Samsung Electronics Co., Ltd. At least penta-sided-channel type of FinFET transistor
JP2005209782A (ja) 2004-01-21 2005-08-04 Toshiba Corp 半導体装置
US7250645B1 (en) 2004-01-22 2007-07-31 Advanced Micro Devices, Inc. Reversed T-shaped FinFET
US7224029B2 (en) * 2004-01-28 2007-05-29 International Business Machines Corporation Method and structure to create multiple device widths in FinFET technology in both bulk and SOI
KR100587672B1 (ko) * 2004-02-02 2006-06-08 삼성전자주식회사 다마신 공법을 이용한 핀 트랜지스터 형성방법
EP1566844A3 (en) 2004-02-20 2006-04-05 Samsung Electronics Co., Ltd. Multi-gate transistor and method for manufacturing the same
US7060539B2 (en) 2004-03-01 2006-06-13 International Business Machines Corporation Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby
JP4852694B2 (ja) * 2004-03-02 2012-01-11 独立行政法人産業技術総合研究所 半導体集積回路およびその製造方法
US6921691B1 (en) 2004-03-18 2005-07-26 Infineon Technologies Ag Transistor with dopant-bearing metal in source and drain
KR100576361B1 (ko) * 2004-03-23 2006-05-03 삼성전자주식회사 3차원 시모스 전계효과 트랜지스터 및 그것을 제조하는 방법
US7141480B2 (en) 2004-03-26 2006-11-28 Texas Instruments Incorporated Tri-gate low power device and method for manufacturing the same
US7154118B2 (en) * 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US8450806B2 (en) 2004-03-31 2013-05-28 International Business Machines Corporation Method for fabricating strained silicon-on-insulator structures and strained silicon-on insulator structures formed thereby
US20050224797A1 (en) 2004-04-01 2005-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS fabricated on different crystallographic orientation substrates
US20050230763A1 (en) 2004-04-15 2005-10-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a microelectronic device with electrode perturbing sill
KR100642632B1 (ko) * 2004-04-27 2006-11-10 삼성전자주식회사 반도체소자의 제조방법들 및 그에 의해 제조된 반도체소자들
US7084018B1 (en) 2004-05-05 2006-08-01 Advanced Micro Devices, Inc. Sacrificial oxide for minimizing box undercut in damascene FinFET
US20050255642A1 (en) * 2004-05-11 2005-11-17 Chi-Wen Liu Method of fabricating inlaid structure
US6864540B1 (en) 2004-05-21 2005-03-08 International Business Machines Corp. High performance FET with elevated source/drain region
KR100634372B1 (ko) * 2004-06-04 2006-10-16 삼성전자주식회사 반도체 소자들 및 그 형성 방법들
US7132360B2 (en) 2004-06-10 2006-11-07 Freescale Semiconductor, Inc. Method for treating a semiconductor surface to form a metal-containing layer
WO2005122276A1 (ja) 2004-06-10 2005-12-22 Nec Corporation 半導体装置及びその製造方法
US7291886B2 (en) 2004-06-21 2007-11-06 International Business Machines Corporation Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs
US8669145B2 (en) 2004-06-30 2014-03-11 International Business Machines Corporation Method and structure for strained FinFET devices
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US20060040054A1 (en) 2004-08-18 2006-02-23 Pearlstein Ronald M Passivating ALD reactor chamber internal surfaces to prevent residue buildup
US7105934B2 (en) 2004-08-30 2006-09-12 International Business Machines Corporation FinFET with low gate capacitance and low extrinsic resistance
US7250367B2 (en) 2004-09-01 2007-07-31 Micron Technology, Inc. Deposition methods using heteroleptic precursors
US7071064B2 (en) 2004-09-23 2006-07-04 Intel Corporation U-gate transistors and methods of fabrication
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7875547B2 (en) 2005-01-12 2011-01-25 Taiwan Semiconductor Manufacturing Co., Ltd. Contact hole structures and contact structures and fabrication methods thereof
US7071047B1 (en) 2005-01-28 2006-07-04 International Business Machines Corporation Method of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regions
US20060172480A1 (en) 2005-02-03 2006-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. Single metal gate CMOS device design
US7238564B2 (en) * 2005-03-10 2007-07-03 Taiwan Semiconductor Manufacturing Company Method of forming a shallow trench isolation structure
US7177177B2 (en) * 2005-04-07 2007-02-13 International Business Machines Corporation Back-gate controlled read SRAM cell
US7429536B2 (en) 2005-05-23 2008-09-30 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7319074B2 (en) 2005-06-13 2008-01-15 United Microelectronics Corp. Method of defining polysilicon patterns
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7352034B2 (en) * 2005-08-25 2008-04-01 International Business Machines Corporation Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures
US7416943B2 (en) * 2005-09-01 2008-08-26 Micron Technology, Inc. Peripheral gate stacks and recessed array gates
US8513066B2 (en) 2005-10-25 2013-08-20 Freescale Semiconductor, Inc. Method of making an inverted-T channel transistor
US7638843B2 (en) 2006-05-05 2009-12-29 Texas Instruments Incorporated Integrating high performance and low power multi-gate devices
US7655989B2 (en) 2006-11-30 2010-02-02 International Business Machines Corporation Triple gate and double gate finFETs with different vertical dimension fins

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9337100B2 (en) 2009-06-03 2016-05-10 Qualcomm Incorporated Apparatus and method to fabricate an electronic device
CN102449769A (zh) * 2009-06-03 2012-05-09 高通股份有限公司 制造电子装置的设备和方法
CN102449769B (zh) * 2009-06-03 2015-11-25 高通股份有限公司 制造电子装置的设备和方法
CN103137621A (zh) * 2011-11-25 2013-06-05 三星电子株式会社 半导体器件及其制造方法
CN103137621B (zh) * 2011-11-25 2017-03-01 三星电子株式会社 半导体器件及其制造方法
US9343559B2 (en) 2011-12-23 2016-05-17 Intel Corporation Nanowire transistor devices and forming techniques
US9012284B2 (en) 2011-12-23 2015-04-21 Intel Corporation Nanowire transistor devices and forming techniques
US9812524B2 (en) 2011-12-23 2017-11-07 Intel Corporation Nanowire transistor devices and forming techniques
CN104011842B (zh) * 2011-12-31 2016-10-26 英特尔公司 用于高鳍状物的硬掩模蚀刻停止层
CN104011842A (zh) * 2011-12-31 2014-08-27 英特尔公司 用于高鳍状物的硬掩模蚀刻停止层
US9923054B2 (en) 2011-12-31 2018-03-20 Intel Corporation Fin structure having hard mask etch stop layers underneath gate sidewall spacers
CN109545802A (zh) * 2018-12-14 2019-03-29 上海微阱电子科技有限公司 一种绝缘体上半导体器件结构和形成方法
CN109545802B (zh) * 2018-12-14 2021-01-12 上海微阱电子科技有限公司 一种绝缘体上半导体器件结构和形成方法

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TW200729407A (en) 2007-08-01
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TWI321830B (en) 2010-03-11
US8193567B2 (en) 2012-06-05
US7479421B2 (en) 2009-01-20
US20090090976A1 (en) 2009-04-09
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