CN101281879B - Double-stage self-aligning contact window and manufacturing method thereof - Google Patents
Double-stage self-aligning contact window and manufacturing method thereof Download PDFInfo
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- CN101281879B CN101281879B CN 200710091610 CN200710091610A CN101281879B CN 101281879 B CN101281879 B CN 101281879B CN 200710091610 CN200710091610 CN 200710091610 CN 200710091610 A CN200710091610 A CN 200710091610A CN 101281879 B CN101281879 B CN 101281879B
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Abstract
A preparation method for double-stage automatic aligning contact window includes: forming a first dielectric layer on a substrate having a contact region; forming a bottom opening in the first dielectric layer corresponding to the contact region; forming a second dielectric layer on the first dielectric layer; forming a upper opening in the second dielectric layer, wherein the upper opening automatically aligns to the bottom opening and communicates with the bottom opening, thereby forming an automatic aligning contact window opening; and finally forming a conductive layer in the automatic aligning contact window opening.
Description
Technical field
The present invention relates to a kind of integrated circuit component and manufacture method thereof, and be particularly related to a kind of double-stage self-aligning contact window (Self-aligned contact, SAC) and manufacture method thereof.
Background technology
Along with the progress of science and technology, the manufacturing of electronic component must improve integration, to meet light, thin, short, the little trend of electronic component.Improve the method for integration, except the size of dwindling semiconductor element itself, also can reach via the distance that reduces between semiconductor element.Yet, no matter be to dwindle itself size of semiconductor element, or dwindle the distance between semiconductor element, some technologic problems all can occur.
With the technique of self-aligning contact window, after the size of contact hole was dwindled, its depth-width ratio (Aspect ratio) increased, and etched difficulty is high, and the space of technique is little.For removing the residue in etch process, guarantee to touch the window opening and can open fully, usually can carry out long over etching, can't open (Contact open) fully to avoid contact window.Yet, please refer to Fig. 1, due to when carrying out photoetching, the time situation of mis-alignment arranged, and the problem (Bowling effect) of enlarging is also arranged at etching dielectric layer 16 when forming contact window 14, therefore, the overlong time of over etching, be easy to make the drift angle 10 of grid 12 out exposed, and cause the problem of grid polycrystalline silicon short circuit (poly short), as shown in the A district.Another side, along with the increase of the depth-width ratio of contact window, metal level also more and more be difficult to fill in contact window in.
U.S. Patent application discloses a kind of manufacture method of self-aligning contact window for No. 2005/0136649.This application case is elder generation forms the different stacking rete of multi-layer material in substrate after, then forms inner insulating layer, afterwards, utilizes the difference of each etched film speed, carries out the single phase self-aligning contact window etch process of source/drain regions.Remove the stacking rete of inner insulating layer and part in technique during, as etch stop layer, be the contact window of T font with the wherein one deck rete in stack layer to form section, expose in this stacking rete the rete as etch stop layer.
United States Patent (USP) discloses a kind of manufacture method of self-aligning contact window for No. 6791190.This patent is to form the conformal lining of layer in substrate, form again inner layer dielectric layer, afterwards, again take conformal lining as etch stop layer, with the inner layer dielectric layer patterning, to form self-aligning contact window opening/without landing contact window (borderless contact opening), be equally in the method with single phase the self-aligning contact window etch process form opening.
On the other hand, in present common semiconductor technology, in order to increase electronics or the hole mobility (mobility) in the raceway groove of metal oxide semiconductor transistor, after being that normally metal oxide semiconductor transistor completes, can form one deck stressor layers in substrate.For the P-type mos transistor, form one deck and have the stressor layers of compression stress (compressive stress) in substrate, can form compression stress along channel direction in the P-type mos transistor.And for the N-type metal oxide semiconductor transistor, form one deck and have the stressor layers of tensile stress (tensile stress) in substrate, can form tensile stress along channel direction in the N-type metal oxide semiconductor transistor.Along with the increase of compression stress or tensile stress, hole or the electronics mobility in raceway groove also with increase, and then increase drive current (drive current) with lift elements usefulness.
Very thick due to stressor layers carries out the etch process of self-aligning contact window with the known method of above-mentioned single phase, still can face above-mentioned problem and have the application region only can be limited in the problem of the source/drain regions that scope is large, accuracy is not high.
Summary of the invention
The invention provides a kind of etch process of self-aligning contact window, with the problem of avoiding contact window to open fully.
The invention provides a kind of etch process of self-aligning contact window, can improve the alignment accuracy space (Aligned accuracy window) between contact hole and grid, solve the short circuit problem that mis-alignment and over etching enlarging cause.
The invention provides a kind of self-aligning contact window technique, can fill up easily conductive layer in contact window.
The invention provides a kind of self-aligning contact window technique, to reduce etched difficulty, increase the space of technique, improving yield (throughput).
The invention provides a kind of self-aligning contact window technique that can integrate with stressor layers.
The present invention proposes a kind of manufacture method of self-aligning contact window.At first, form the first dielectric layer in the substrate with contact zone.Then, form lower openings in the first dielectric layer, it is corresponding with the contact zone.Afterwards, form the second dielectric layer on the first dielectric layer.Then, form upper opening in the second dielectric layer, it is aligned with lower opening and be communicated with it and consist of the self-aligning contact window opening voluntarily.Then, form conductive layer in the self-aligning contact window opening.
Described according to the embodiment of the present invention, in the manufacture method of above-mentioned self-aligning contact window, form in the step of lower openings in the first dielectric layer, formed lower openings exposes the part of first dielectric layer on the contact zone, and when forming the step of upper opening, also comprise the first dielectric layer of removing this lower openings bottom, expose the contact zone.
Described according to the embodiment of the present invention, in the manufacture method of above-mentioned self-aligning contact window, the first dielectric layer comprises stressor layers.The material of stressor layers comprises silicon nitride.Be with timing mode etching stressor layers in the step of formation lower openings in the first dielectric layer, make the bottom of formed lower openings still have the part stressor layers to be covered on the contact zone.
Described according to the embodiment of the present invention, in the manufacture method of above-mentioned self-aligning contact window, the first dielectric layer from bottom to top comprises etch stop layer, endpoint detecting layer and stressor layers.The material of etch stop layer comprises silicon nitride, and the material of endpoint detecting layer comprises silica, and the material of stressor layers comprises silicon nitride.Form in the step of lower openings in the first dielectric layer, lower openings is to expose stressor layers, endpoint detecting layer or etch stop layer.
Described according to the embodiment of the present invention, in the manufacture method of above-mentioned self-aligning contact window, the first dielectric layer from bottom to top comprises endpoint detecting layer and stressor layers.The material of endpoint detecting layer comprises silica, and the material of stressor layers comprises silicon nitride.Form in the step of lower openings in the first dielectric layer, lower openings is to expose stressor layers or endpoint detecting layer.
Described according to the embodiment of the present invention, the manufacture method of above-mentioned self-aligning contact window is after also being included in the formation lower openings, before forming the second dielectric layer, in the sidewall formation lining of lower openings.The material of lining comprises silica or silicon oxynitride.
Described according to the embodiment of the present invention, in the manufacture method of above-mentioned self-aligning contact window, the material of the second dielectric layer is the group that silica, phosphorosilicate glass, boron-phosphorosilicate glass and fluorine doped-glass and the combination thereof of the silica that is selected from aumospheric pressure cvd, high-density plasma vapour deposition forms.
Described according to the embodiment of the present invention, in the manufacture method of above-mentioned self-aligning contact window, self-aligning contact window is the contact hole of source/drain regions, the contact hole of grid, or the shared contact hole of source/drain regions and grid.
Described according to the embodiment of the present invention, in the manufacture method of above-mentioned self-aligning contact window, lower openings is different from the size of upper opening.
Described according to the embodiment of the present invention, in the manufacture method of above-mentioned self-aligning contact window, the size of lower openings less than with the size of upper opening.
The present invention proposes a kind of self-aligning contact window, and it comprises bottom contact hole and the top contact hole of the dielectric layer that is arranged in substrate, its middle and upper part contact hole be positioned on the contact hole of bottom and with its electric connection, and the top contact hole is different from the size of bottom contact hole.
Described according to the embodiment of the present invention, in above-mentioned self-aligning contact window, the size of top contact hole is greater than the size of bottom contact hole.
Described according to the embodiment of the present invention, in above-mentioned self-aligning contact window, self-aligning contact window is the contact hole that is connected with source/drain regions, the contact hole that is connected with grid, or is the shared contact hole of source/drain regions and grid.
Described according to the embodiment of the present invention, above-mentioned self-aligning contact window also comprises lining, enclose outside the contact hole of bottom and dielectric layer between.
Described according to the embodiment of the present invention, in above-mentioned self-aligning contact window, the material of lining comprises silica or silicon oxynitride.
Described according to the embodiment of the present invention, in above-mentioned self-aligning contact window, the first dielectric layer comprises stressor layers.The material of stressor layers comprises silicon nitride.
Described according to the embodiment of the present invention, in above-mentioned self-aligning contact window, the first dielectric layer from bottom to top comprises etch stop layer, endpoint detecting layer and stressor layers.The material of etch stop layer comprises silicon nitride, and the material of endpoint detecting layer comprises silica, and the material of stressor layers comprises silicon nitride.
Described according to the embodiment of the present invention, in above-mentioned self-aligning contact window, the first dielectric layer from bottom to top comprises endpoint detecting layer and stressor layers.The material of endpoint detecting layer comprises silica, and the material of stressor layers comprises silicon nitride.
Self-aligning contact window technique of the present invention can be improved the alignment accuracy space between contact hole and grid, solves the short circuit problem that mis-alignment and over etching enlarging cause.
Again, the present invention adopts the segmentation etching, can reduce etched difficulty, avoids contact window to open incomplete problem, and therefore, the present invention can increase the space of technique, improving yield.
In addition, due to the size of the upper opening of the contact hole size greater than lower openings, therefore, conductive layer can be easy to fill in contact window in.
Moreover, form lining in lower openings, can make technique can adopt photoetching grade now and produce less opening size.
On the other hand, the present invention can be combined with the stressor layers that widely adopts now.
For above and other purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperation accompanying drawing are described in detail below.
Description of drawings
Fig. 1 illustrates the schematic diagram of known a kind of contact hole.
Fig. 2 A to Fig. 2 F is the flow process profile of the manufacture method of a kind of semiconductor element of illustrating according to the embodiment of the present invention.
Fig. 3 A to Fig. 3 H is the flow process profile of the manufacture method of the another kind of semiconductor element that illustrates according to the embodiment of the present invention.
Description of reference numerals
10: grid drift angle 12: grid
14: contact hole 16,122,130: dielectric layer
100: substrate 102,103: transistor
104: gate dielectric layer 106: grid
110: source/drain regions 114: clearance wall
116: etch stop layer 118: the endpoint detecting layer
120: stressor layers 122: dielectric layer
124,146: photoresist layer 136,166,186: lower openings
138,168,188: upper opening 140,170: the self-aligning contact window opening
150: conformal lining material layer 150a: lining
190: aim at voluntarily contact window 142,172 altogether: self-aligning contact window
192: aim at voluntarily contact hole altogether
Embodiment
Embodiment one
Fig. 2 A to Fig. 2 F is the flow process profile of the manufacture method of a kind of semiconductor element of illustrating according to the embodiment of the present invention.
Please refer to Fig. 2 A, at first substrate 100 is provided.This substrate 100 is for example silicon base, as N-type silicon base or P type silicon base.Certainly, substrate 100 can be also that the substrate of silicon etc. is arranged on insulating barrier.Transistor 102 and 103 have been formed with in this substrate 100. Transistor 102 and 103 is for example N NMOS N-channel MOS N conductor element (NMOS) or P-channel metal-oxide-semiconductor conductor element (PMOS).
Source/drain regions 110 is to be arranged in the substrate of grid 106 both sides.The dopant of source/drain regions 110 can be the N-type dopant, can be also P type dopant.The material of source/drain regions 110 is for example take semi-conducting material or semiconducting compound as main material.Semi-conducting material is for example silicon.The material of semiconducting compound is for example germanium silicide or carborundum.
In one embodiment, also comprising respectively metal silicide layer (not illustrating) on the surface of grid 106 and on source/drain regions 110.Metal silicide layer comprises the metal silicide layer of refractory metal, is for example one of them of silicide of the alloy of nickel, cobalt, titanium, copper, molybdenum, tantalum, tungsten, erbium, zirconium, platinum and these metals.
Please continue the A with reference to Fig. 2, form dielectric layer 122 in substrate 100.In one embodiment, dielectric layer 122 is made of stressor layers 120, and this stressor layers 120 can increase drive current, lift elements usefulness.For P type channel metal oxide semiconductor transistor, stressor layers 120 is compressive stress layers, can form compression stress along channel direction in P type channel metal oxide semiconductor transistor, and the mobility of hole in raceway groove increased.And for the N-type channel metal oxide semiconductor transistor, stressor layers 120 is tension stress layer, can form tensile stress along channel direction in the N-type channel metal oxide semiconductor transistor, and the mobility of electronics in raceway groove increased.The material of stressor layers 120 is for example silicon nitride, and the method for formation is for example chemical vapour deposition technique.
In another embodiment, dielectric layer 122 comprises that also endpoint detecting layer 118 is positioned at the below of stressor layers 120 except comprising above-mentioned stressor layers 120.The material of endpoint detecting layer 118 is different from the material of stressor layers 120, in etched process, has different etch-rates from stressor layers 120.The material of endpoint detecting layer 118 is for example silica, and the method for its formation is for example chemical vapour deposition technique.
In another embodiment, dielectric layer 122 also comprises one deck etch stop layer 116 except comprising above-mentioned stressor layers 120, endpoint detecting layer 118, be positioned at the below of endpoint detecting layer 118.The material of etch stop layer 116 is different from the material of endpoint detecting layer 118, in etched process, has different etch-rates from endpoint detecting layer 118.The material of etch stop layer 116 is for example silicon nitride, and the method for its formation is for example chemical vapour deposition technique.
, please continue with reference to Fig. 2 A, form one deck patterning photoresist layer 124 on dielectric layer 122 thereafter.
Afterwards, please refer to Fig. 2 B, carry out the Patternized technique of the phase I of dielectric layer.Take patterning photoresist layer 124 as etching mask; etching dielectric layer 122; to form lower openings 136,166,186 in dielectric layer 122; it is corresponding with predetermined contact zone; and have the dielectric layer 122 of part to cover; namely corresponding but do not expose the grid 106 of source/drain regions 110, transistor 103 and the grid 106 of transistor 102 respectively, with in follow-up etch process as protective layer, avoid suffering etched destruction.
When dielectric layer 122 is when being made of stressor layers 120, carries out formed lower openings 136 after etch process, 166 and 186 bottoms and still have stressor layers 120 to stay on the grid 106 of the grid 106 of source/drain regions 110, transistor 103 and transistor 102.
When dielectric layer 122 is when being made of stressor layers 120 and 118, endpoint detecting layer, etch process can with endpoint detecting layer 118 as etch stop layer, make formed lower openings 136,166 and 186 bottoms expose endpoint detecting layer 118.Or, etch process can utilize timing controlled, and stop at stressor layers 120, make formed lower openings 136,166 and 186 bottoms still have stressor layers 120 to stay on the grid 106 of the grid 106 of source/drain regions 110, transistor 103 and transistor 102.
When dielectric layer 122 is when being made of stressor layers 120, endpoint detecting layer 118 and etch stop layer 116, etch process can be as the above, make formed lower openings 136,166 and 186 bottoms expose endpoint detecting layer 118, or expose stressor layers 120.Also or, expose etch stop layer 116.
The method of etching dielectric layer 122 can adopt anisotropic etching process, is for example with fluorohydrocarbon or the known various gases dry method etch technology as etch gas source.
, please refer to Fig. 2 C, remove patterning photoresist layer 124 thereafter.The method that removes patterning photoresist layer 124 for example wet method removes method, or dry method removes method such as Oxygen plasma ashing method.Then, form another layer dielectric layer 130 in substrate 100.Dielectric layer 130 is made of simple layer, or is made of two or more material layers.In the present embodiment, be that dielectric layer 130 with individual layer illustrates.The material of dielectric layer 130 is such as being the silica of aumospheric pressure cvd, silica, phosphorosilicate glass, boron-phosphorosilicate glass or the fluorine doped-glass etc. of high-density plasma vapour deposition.
Afterwards, please refer to Fig. 2 D, carry out the Patternized technique of the second stage of dielectric layer, form patterning photoresist layer 146 on dielectric layer 130.Then, take patterning photoresist layer 146 as etching mask, residual dielectric layer 122 is as etch stop layer, and etching dielectric layer 130 is to form upper opening 138,168 and 188 in dielectric layer 130.Upper opening 138 is aligned with lower opening 136 voluntarily, and coupled logical; Upper opening 168 is aligned with lower opening 166 voluntarily, and coupled logical; Upper opening 188 is aligned with lower opening 168 voluntarily, and coupled logical.In forming upper opening 138,168 and 188 etching process; can be take stressor layers 120, endpoint detecting layer 118 or the etch stop layer 116 of dielectric layer 122 as stop layer; protect source/drain regions 110 and the grid 106 of its below, avoid suffering etched destruction.The method of etching dielectric layer 130 can adopt anisotropic etching process, is for example with fluorohydrocarbon or the known various gases dry method etch technology as etch gas source.
Continue it, please refer to Fig. 2 E, remove the dielectric layer 122 of lower openings 136,166,186 bottoms, with the grid 106 and source/drain regions 110 of the grid 106 that exposes source/drain regions 110, transistor 103 and transistor 102, that completes that self-aligning contact window opening 170 that the self-aligning contact window opening 140 that is made of upper opening 138 and lower openings 136, upper opening 168 and lower openings 166 consist of and upper opening 188 and lower openings 186 consist of aims at common contact window 190 voluntarily.The method that removes the dielectric layer 122 of lower openings 136,166,186 bottoms can adopt anisotropic etching process, is for example with fluorohydrocarbon or the known various gases dry method etch technology as etch gas source.
Afterwards, remove patterning photoresist layer 146.The method that removes patterning photoresist layer 146 for example wet method removes method, or dry method removes method such as Oxygen plasma ashing method.
Afterwards, please refer to Fig. 2 F, at self-aligning contact window opening 140 and 170 and aim at voluntarily altogether and insert conductive layer in contact window 190, to form self-aligning contact window 142 and 172 and aim at voluntarily common contact hole 192.The formation method of conductive layer can be in substrate 100 sequentially forms and covers dielectric layer 130 and insert self-aligning contact window opening 140 and 170 and the conductive material layer (not illustrating) of aiming at voluntarily common contact window 190, afterwards, utilize chemical mechanical polishing method or etch-back method, remove the part that covers dielectric layer 130, complete self-aligning contact window 142 and 172 and the making of aiming at voluntarily common contact hole 192.The material of conductive material layer is for example tungsten metal, copper metal or its alloy, or the polysilicon of doping.Usually, except aforesaid material, conductive material layer also comprises one deck barrier layer or one deck adhesion coating, and its material is for example titanium, tantalum, titanium nitride, tantalum nitride or its combination.
Embodiment two
Fig. 3 A to 3H is the flow process profile of the manufacture method of the another kind of semiconductor element that illustrates according to the embodiment of the present invention.
Please refer to Fig. 3 A and 3B, according to the described method of embodiment, dielectric layer 122 in substrate 100 is carried out the Patternized technique of phase I, with form in dielectric layer 122 lower openings 136 corresponding with source/drain regions 110, with lower openings 166 corresponding to the grid 106 of transistor 103 and the lower openings 186 corresponding with the source/drain regions 110 of the grid 106 of transistor 102 and transistor 103.
Please refer to Fig. 3 C, after removing photoresist layer 124, first form conformal lining material layer 150 in substrate 100, cover dielectric layer 122 and lower openings 136,166 and 186 sidewall and bottom.The material of lining material layer 150 comprises silica or silicon oxynitride, and the method for formation is for example chemical vapour deposition technique.
Afterwards, please refer to Fig. 3 D, conformal lining material layer 150 is carried out anisotropic etching process, stay the part that is positioned at lower openings 136,166 and 186 sidewalls, to form lining 150a.Lining 150a can be used for dwindling lower openings 136,166 and 186 size.That is lower openings 136,166 and 186 formation method can adopt existing photoetching process to expose, develop, and after carrying out etch process, then dwindle lower openings 136,166 and 186 size by the formation of lining 150a.
Please refer to Fig. 3 E to 3H, according to the method for above-described embodiment one, form dielectric layer 130.Then, as etch stop layer, and carry out the Patternized technique of second stage with residual dielectric layer 122, to form upper opening 138,168 and 188 in dielectric layer 130.Afterwards, remove the dielectric layer 122 of lower openings 136,166,186 bottoms, with the grid 106 and source/drain regions 110 of the grid 106 that exposes source/drain regions 110, transistor 103 and transistor 102, that completes that self-aligning contact window opening 170 that the self-aligning contact window opening 140 that is made of upper opening 138 and lower openings 136, upper opening 168 and lower openings 166 consist of and upper opening 188 and lower openings 186 consist of aims at common contact window 190 voluntarily.Afterwards, then in self-aligning contact window opening 140 and 170 and aim at voluntarily altogether and insert conductive layer in contact window 190, to form self-aligning contact window 142 and 172 and aim at voluntarily common contact hole 192.
The self-aligning contact window of the embodiment of the present invention is made of bottom contact hole and top contact hole.The size of top contact hole is greater than the size of bottom contact hole.In another embodiment, enclose outside the contact hole of bottom and dielectric layer between also comprise lining it can be used for dwindling the size of formed lower openings, make technique can adopt photoetching grade now and produce less opening size.
In sum, to carry out etching with two stages or multistage in self-aligning contact window technique of the present invention, can improve the alignment accuracy space between contact hole and grid, avoid the wrong grid that causes with over etching for a long time and the short circuit problem between source/drain regions aimed at.
Moreover the present invention adopts the segmentation etching, and because the depth-width ratio of the contact window of every one-phase diminishes, therefore, etched difficulty step-down can avoid contact window to open incomplete problem, the output of lifting process.
Again, due to the size of the upper opening of the contact hole size greater than lower openings, therefore, conductive layer can be easy to fill in contact window in.
In addition, form lining in lower openings, can make technique can adopt photoetching grade now and produce less opening size.
On the other hand, the present invention can be combined with the stressor layers that widely adopts now.Can be used as the ground floor dielectric layer of aligned with lower opening voluntarily in this stressor layers, and can be used as the etch stop layer of the etch process of follow-up upper opening.
Although the present invention discloses as above with preferred embodiment; so it is not to limit the present invention; those skilled in the art without departing from the spirit and scope of the present invention, when can do a little change and retouching, so protection scope of the present invention is when looking accompanying being as the criterion that claim defines.
Claims (16)
1. the manufacture method of a double-stage self-aligning contact window, comprise
Substrate is provided, has the contact zone in this substrate;
Form the first dielectric layer in this substrate;
Form lower openings in this first dielectric layer, it is corresponding with this contact zone;
Form the second dielectric layer on this first dielectric layer, this second dielectric layer forms can insert this lower openings simultaneously;
Take this first dielectric layer as etch stop layer, this second dielectric layer of etching, and this second dielectric layer of etching can remove the part of inserting this lower openings simultaneously, only to form upper opening in this second dielectric layer, it is aimed at voluntarily this lower openings and is communicated with it and consists of the self-aligning contact window opening; And
Form conductive layer in this self-aligning contact window opening,
Wherein form in the step of this lower openings in this first dielectric layer, formed this lower openings exposes this first dielectric layer of part on this contact zone, and when forming the step of this upper opening, also comprise this first dielectric layer of removing this lower openings bottom, expose this contact zone.
2. the manufacture method of double-stage self-aligning contact window as claimed in claim 1, wherein this first dielectric layer comprises stressor layers.
3. the manufacture method of double-stage self-aligning contact window as claimed in claim 2, wherein the material of this stressor layers comprises silicon nitride.
4. the manufacture method of double-stage self-aligning contact window as claimed in claim 2, be wherein with this stressor layers of timing mode etching in the step of this lower openings of formation in this first dielectric layer, make the bottom of formed this lower openings still have this stressor layers of part to be covered on this contact zone.
5. the manufacture method of double-stage self-aligning contact window as claimed in claim 1, wherein this first dielectric layer from bottom to top comprises etch stop layer, endpoint detecting layer and stressor layers.
6. the manufacture method of double-stage self-aligning contact window as claimed in claim 5, wherein the material of this etch stop layer comprises silicon nitride, and the material of this endpoint detecting layer comprises silica, and the material of this stressor layers comprises silicon nitride.
7. the manufacture method of double-stage self-aligning contact window as claimed in claim 5, wherein form in this first dielectric layer in the step of this lower openings, and this lower openings is to expose this stressor layers, this endpoint detecting layer or this etch stop layer.
8. the manufacture method of double-stage self-aligning contact window as claimed in claim 1, wherein this first dielectric layer from bottom to top comprises endpoint detecting layer and stressor layers.
9. the manufacture method of double-stage self-aligning contact window as claimed in claim 8, wherein the material of this endpoint detecting layer comprises silica, the material of this stressor layers comprises silicon nitride.
10. the manufacture method of double-stage self-aligning contact window as claimed in claim 8, wherein form in this first dielectric layer in the step of this lower openings, and this lower openings is to expose this stressor layers or this endpoint detecting layer.
11. the manufacture method of double-stage self-aligning contact window as claimed in claim 1 also is included in after this forms this lower openings, before forming this second dielectric layer, forms lining at the sidewall of this lower openings.
12. the manufacture method of double-stage self-aligning contact window as claimed in claim 11, wherein the material of this lining comprises silica or silicon oxynitride.
13. the manufacture method of double-stage self-aligning contact window as claimed in claim 1, wherein the material of this second dielectric layer is the group that silica, phosphorosilicate glass, boron-phosphorosilicate glass and fluorine doped-glass and the combination thereof of the silica that is selected from aumospheric pressure cvd, high-density plasma vapour deposition forms.
14. the manufacture method of double-stage self-aligning contact window as claimed in claim 1, wherein this self-aligning contact window is the contact hole of source/drain regions, the contact hole of grid, or the shared contact hole of source/drain regions and grid.
15. the manufacture method of double-stage self-aligning contact window as claimed in claim 1, wherein this lower openings is different from the size of this upper opening.
16. the manufacture method of double-stage self-aligning contact window as claimed in claim 15, wherein the size of this lower openings less than with the size of this upper opening.
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| CN 200710091610 CN101281879B (en) | 2007-04-03 | 2007-04-03 | Double-stage self-aligning contact window and manufacturing method thereof |
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| CN 200710091610 CN101281879B (en) | 2007-04-03 | 2007-04-03 | Double-stage self-aligning contact window and manufacturing method thereof |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4996167A (en) * | 1990-06-29 | 1991-02-26 | At&T Bell Laboratories | Method of making electrical contacts to gate structures in integrated circuits |
| US6165880A (en) * | 1998-06-15 | 2000-12-26 | Taiwan Semiconductor Manufacturing Company | Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4996167A (en) * | 1990-06-29 | 1991-02-26 | At&T Bell Laboratories | Method of making electrical contacts to gate structures in integrated circuits |
| US6165880A (en) * | 1998-06-15 | 2000-12-26 | Taiwan Semiconductor Manufacturing Company | Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits |
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| CN101281879A (en) | 2008-10-08 |
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