CN101208805A - 纳米尺度沟道晶体管的块接触结构 - Google Patents

纳米尺度沟道晶体管的块接触结构 Download PDF

Info

Publication number
CN101208805A
CN101208805A CNA200680023301XA CN200680023301A CN101208805A CN 101208805 A CN101208805 A CN 101208805A CN A200680023301X A CNA200680023301X A CN A200680023301XA CN 200680023301 A CN200680023301 A CN 200680023301A CN 101208805 A CN101208805 A CN 101208805A
Authority
CN
China
Prior art keywords
parallel
semiconductor
source
region
spacing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA200680023301XA
Other languages
English (en)
Other versions
CN101208805B (zh
Inventor
M·拉多萨夫耶维克
A·马祖姆达
B·S·多伊尔
J·卡瓦利罗斯
M·L·多茨
J·K·布拉斯克
U·沙
S·达塔
R·S·曹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN101208805A publication Critical patent/CN101208805A/zh
Application granted granted Critical
Publication of CN101208805B publication Critical patent/CN101208805B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41733Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41791Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00Manufacture or treatment of nanostructures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L2029/7858Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78681Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys

Abstract

一种纳米尺度沟道器件的接触体系结构,具有耦合并延伸在具有多个并行半导体本体的源区和漏区之间的接触结构。所述接触结构能够接触具有亚光刻间距的并行半导体本体。

Description

纳米尺度沟道晶体管的块接触结构
技术领域
本发明涉及半导体集成电路制造领域,特别是涉及纳米尺度(nanoscale)沟道器件的接触结构。
背景技术
半导体器件的发展和对半导体器件小型化的不断追求导致在制作更小的结构时需要更好的制作过程,因为更小的器件通常等同于更快的切换时间,这会产生提高的性能。
为了获得该提高的器件性能,需要更小的器件沟道长度并且提出了在大块硅衬底和绝缘硅(SOI)衬底上的许多非平面器件配置如双栅,FinFET,三栅和ω栅。为了制作具有任意大驱动电流的纳米尺度晶体管,器件结构可包括附加的多个半导体本体(body)或指状部件(finger),从而产生多个并行沟道。图1是绝缘硅102上的多沟道三栅晶体管的透视图解。多沟道晶体管100包括具有绝缘层103的单晶硅衬底101,如在其上形成的埋氧层。在绝缘层上,多个半导体本体或指状部件105按图1所示的方式形成。在多个半导体本体105上形成栅绝缘层112,在栅绝缘层112上形成栅电极113,箍缚(strap)在多个半导体本体105上。源区116和漏区117在单晶半导体层中沿栅电极113的横向相反面来形成。
如图1所示,对于典型的三栅器件,各个半导体本体105具有在其上表面和侧壁上形成的栅绝缘层112。在每个半导体本体105上的每个栅绝缘层112上和附近形成栅电极113。如图1所示,各个半导体本体105还包括在半导体本体105中于栅电极113的相反面上形成的源区116和漏区117。如图1所示,半导体本体105的源区116和漏区117通过半导体材料电耦合在一起,所述半导体材料用于形成半导体本体105以形成源着陆垫(source landing pad)118和漏着陆垫(drain landing pad)119。源着陆垫118和漏着陆垫119各通过金属接触结构123电耦合到用于将各种晶体管100电互连在一起形成功能电路的互连金属(如金属1,金属2,金属3......)的上层。如图1所示,为了维持整个晶体管的并行电路结构,为每个半导体本体105提供了一对金属接触(contact)结构123,为源区116提供了第一金属接触结构以及为漏区117提供了第二金属接触。
金属接触结构如图1所示,随着半导体本体105的间距(pitch)的减小,金属接触结构123的间距110也一定减小。如果金属接触结构123的间距110没有随着并行半导体器件的间距的减小而减小,金属接触结构的总电阻、外部电阻(Rext),就会成为器件100的整个寄生电阻的重要部分。因此,金属接触结构123由金属接触结构123的最小光刻间距所制约,从而造成在金属接触结构123的最小光刻间距之下,随着半导体本体105的间距减小,Rext增大。
附图说明
图1是传统多沟道非平面晶体管的透视图的图解说明。
图2A是根据本发明具有金属接触结构的多沟道非平面晶体管的透视图的图解说明。
图2B是根据本发明具有金属接触结构的多沟道非平面晶体管的透视图的图解说明。
图2C是根据本发明具有金属接触结构的多沟道非平面晶体管的透视图的图解说明。
图2D是根据本发明具有金属接触结构的多沟道非平面晶体管的透视图的图解说明。
图3A-3L是制作根据本发明的具有金属接触结构的多沟道非平面晶体管的方法的透视图和横截面视图的图解说明。
具体实施方式
描述了多沟道非平面晶体管的一种新颖的接触结构和它的制作方法。为了提供对本发明的充分理解,在下面的描述中,阐述了许多具体细节,如具体的材料,尺寸和工艺等。为了避免不必要地使本发明变得不清楚,在另一些实例中,没有对公知的半导体工艺和制造技术进行特别详细的描述。
本发明的实施例包括器件接触结构,其中矩形金属结构与非平面晶体管的源区或漏区接触,所述非平面晶体管具有多个半导体本体,所述本体具有由单个栅电极并行控制的沟道。本发明的实施例包括器件接触结构,其中至少一个金属漏接触结构耦合到并延伸在多个半导体本体的漏区之间,以及至少一个金属接触结构耦合到并延伸在多沟道非平面晶体管的多个半导体本体的源区之间。因为矩形块接触结构与多个半导体本体接触,多沟道非平面器件的外部电阻(Rext)随着多个半导体器件的源区端和漏区端的电流密集度的降低而减小。这种方式下,矩形块结构增加了晶体管的切换(switching)速度。
通常,单个晶体管器件提供了足够的绝对电流来驱动电路逻辑功能。然而,随着晶体管沟道宽度缩小到纳米大小,单个晶体管携带的绝对电流也会减小。所以,虽然纳米尺度大小的器件提高了速度,它们的绝对电流却不再足以驱动大的负载,从而限制了单个纳米晶体管的应用。因此,将具有纳米沟道的纳米尺度器件配置且并行运行,使一组纳米器件能够以单个纳米沟道器件的速度运行并提供足够的绝对电流来驱动大的负载,这是很有利的。为了达到必要的驱动电流而并行运行的纳米尺度器件需要一个形状因素,它至少要与提供等量绝对电流的较大单个晶体管器件一样小。这个要求对于避免为提高纳米沟道器件的切换速度而牺牲的逻辑级集成是必要的,并可以被描述为布局(layout)效率。布局效率是并行非平面器件布局的绝对载流宽度(current carrying width)(Z)与占用相同布局宽度的典型平面器件的绝对载流宽度的比值。因为单个非平面纳米尺度晶体管相对于占用相同布局宽度的单个平面纳米尺度晶体管来说,增加了有效载流宽度(Z),所以单个非平面器件的布局效率明显高于100%。然而,如前所述,非平面结构实现的尺寸缩小导致相对低的绝对电流,很多这种非平面器件可能以并行配置方式来运行。除非并行非平面纳米尺度晶体管间的间距小于平面晶体管的最小间距,描述单个非平面器件所需的布局宽度才能够将布局效率减小到100%以下。因此,除非非平面器件的间距与沟道的尺寸按比例缩小,否则并行非平面器件的总载流宽度仍然小于单个平面器件的总载流宽度。因为,典型的平面晶体管具有与金属接触部件(feature)的最小光刻间距相似的沟道间距,所以为了确定单个纳米尺度晶体管本体,可能必须要依赖非光刻构成技术,如间隔区(spacer)和自调整,将非平面纳米尺度晶体管的间距减小到亚光刻(sub-lithographic)级别。这些技术的应用使得纳米尺度沟道器件的布局效率明显高于100%,然而因为平面晶体管总是有最小刻蚀间距,就不可能描述或光刻印刷每个晶体管沟道的单个源接触结构和漏接触结构。此外,即使非平面晶体管器件通过传统的光刻技术来印刷,那也可能是不切实际的昂贵或者很难达到传统接触结构所要求的严格尺寸控制。与传统的接触结构不同,本发明的实施例不受最小光刻间距的限制,不需要在多个纳米尺度晶体管之间共享最小的接触结构。本发明的实施例减小了通过金属接触结构的电流并降低了器件的Rext,从而增加了器件的切换速度。
图2A说明了根据本发明的一个实施例的有金属接触结构的多沟道非平面晶体管200的实例。尽管图2A所示的非平面晶体管200是三栅器件,其它非平面多沟道晶体管的设计,例如但不局限于双栅,ω栅,半导体纳米线,碳纳米管器件,也是本发明的实施例。多沟道非平面晶体管200形成于衬底202上。在本发明的某些实施例中,衬底202是包括在其上形成绝缘层203、如二氧化硅膜层的较低单晶硅衬底201的绝缘衬底。然而,多沟道非平面晶体管200可以形成于任何公知的绝缘衬底上,例如可由二氧化硅,氮化物,碳化物和刚玉形成的衬底。在本发明的某些实施例中,衬底202可以是“大块”半导体衬底,例如但不限于单晶硅衬底和砷化镓衬底。“大块”半导体衬底只是没有绝缘层203。在本发明的一个实施例中,衬底202是具有掺杂外延层的硅半导体衬底,所述外延层具有p型或n型传导性,浓度级别在每立方厘米1×1016至1×1019个原子之间。
在本发明的一个实施例中,多沟道非平面晶体管200包括在绝缘衬底202的绝缘体203上形成的多个半导体本体205。虽然图2A示出了本发明的三栅实施例,但应该明白非平面晶体管的其它实施例也是可能的,例如但不限于双栅、FinFET、ω栅、碳纳米管的设计。半导体器件205可以由任何公知的半导体材料形成,如硅(Si)、锗(Ge)、硅锗(SixGey)、砷化镓(GaAs)、锑化铟(InSb)、磷化镓(GaP)、锑化镓(GaSb)、磷化铟(InP)和碳纳米管。半导体本体205可以由任何公知的材料形成,这种材料可以通过应用外部电流控制可逆地从绝缘状态改变到导电状态。在希望晶体管200有最好的电气性能时,半导体器件205理想地是单晶膜层。例如,当晶体管200用于高性能应用中时,例如在高密度电路中,如微处理器,半导体本体205是单晶膜层。然而,当晶体管200用于要求不太高的性能的应用中时,如液晶显示中,半导体器件205可以是多晶膜层。在本发明的一个实施例中,绝缘体203使半导体器件205和单晶硅衬底201隔离。在本发明的一个实施例中,半导体本体205是单晶硅膜层。在用到“大块”衬底的本发明的一个实施例中,半导体本体205在“大块”半导体衬底的上部区域中形成。半导体器件205具有一对横向相反的侧壁206和207,它们被分开确定单个半导体本体或指状部件宽度的距离。此外,半导体本体205具有上表面208,对着衬底202上形成的下表面。上表面208和下表面之间的距离确定单个半导体本体的高度。在本发明的一个实施例中,单个本体高度基本上等于单个半导体本体宽度。在本发明的一个实施例中,单个半导体本体205的宽度和高度小于30纳米,理想的是小于20纳米。在本发明的一个实施例中,单个半导体本体的高度在单个半导体本体宽度的一半到两倍之间。在本发明的一个实施例中,两个相邻半导体器件之间的距离小于30纳米,理想的是小于20纳米。在本发明的一个实施例中,两个相邻的半导体器件间的距离小于单个半导体本体的宽度。在本发明的一个实施例中,半导体器件的间距,半导体本体的侧壁206和相邻的半导体本体的侧壁206之间的距离,是亚光刻的。在本发明的一个实施例中,半导体器件间的间距小于110纳米。
多沟道非平面晶体管200具有栅绝缘层212。如图2A所示,栅绝缘层212形成于半导体本体205上并环绕其三个面。如图2A所示,栅绝缘层212在半导体本体205的侧壁206上或邻近的地方、其上表面208上、其侧壁207上或邻近的地方形成。栅绝缘层212可以是任何公知的电介质层。在本发明的一个实施例中,栅绝缘层是二氧化硅(SiO2)、氮氧化硅(SiOxNy)、或氮化硅(Si3N4)电介质层。在本发明的一个实施例中,栅绝缘层212是氮氧化硅形成的厚度在5-20之间的膜层。在本发明的一个实施例中,栅绝缘层212是高k栅绝缘层,如氧化金属电介质层,例如但不限于五氧化二钽、二氧化钛、二氧化铪、氧化锆、氧化铝。栅绝缘层212可以是高K电介质的其它类型,例如但不限于钛酸锆(PZT)。
如图2A所示,多沟道非平面晶体管200具有栅电极213。如图2A所示,栅电极213在栅绝缘层212上和其周围形成。栅电极213形成于栅绝缘层212上或其附近,栅绝缘层212形成于半导体本体205的每一个的侧壁206上,栅电极213形成于栅绝缘层212上,栅绝缘层212形成于半导体本体205的每一个的上表面208上,以及栅电极213形成于栅绝缘层212上或其附近,栅绝缘层212形成于半导体本体205的每一个的侧壁207上。栅电极213具有一对横向相反的侧壁,它们被分开确定晶体管200的栅长度(Lg)的距离。在本发明的一个实施例中,栅电极213的横向相反的侧壁在垂直于半导体本体205的横向相反的侧壁206和207的方向上延伸。
栅电极213可由任何合适的栅电极材料构成。在本发明的一个实施例中,栅电极213由掺杂浓度在每立方厘米1×1019个原子到1×1020个原子的多晶硅构成。在本发明的一个实施例中,栅电极可以是金属栅电极,例如但不限于钨,钽,钛,镍,钴,铝,以及对应的氮化物和硅化物。在本发明的一个实施例中,栅电极是由碳纳米管形成的。在本发明的一个实施例中,栅电极由中间带(mid-gap)逸出功在4.6-4.9eV之间的材料形成。应该明白,栅电极213不一定是单一的物质,而可以是薄膜层的复合堆叠,例如但不限于多晶硅/金属电极或金属/多晶硅电极。
如图2A所示,多沟道非平面晶体管200具有半导体本体205的源区216和漏区217。如图2A所示,源区216和漏区217在半导体本体205中于栅电极213的相反面上形成。所形成的源区216和漏区217具有相同的传导性类型,例如n型或p型传导性。在本发明的一个实施例中,源区216和漏区217的掺杂浓度为每立方厘米1×1019到1×1020个原子。所形成的源区216和漏区217可具有均匀的浓度,或者可包括不同浓度或掺杂分布的子区域,例如上表面(例如源延伸区/漏延伸区)。
在本发明的一个实施例中,源区216和漏区217可包括形成于半导体器件205或其周围的硅片或其它半导体膜层。例如,半导体膜层可以是硅膜层或硅合金如锗化硅(SixGey),从而形成“提高的(raised)”源区和漏区。在本发明的一个实施例中,硅化物的膜层,例如但不限于硅化钛,硅化镍,以及硅化钴,形成于源区216和漏区217上。在本发明的一个实施例中,硅膜层直接形成于半导体器件205的上表面208上。在本发明的一个实施例中,源区216和漏区217是完全硅化的(FUSI)。
如图2A所示,在本发明的一个实施例中,半导体器件205的源区216和漏区217通过用于形成半导体本体205的材料电耦合在一起,以形成共同的源轨道(rail)或源着陆垫218和共同的漏轨道或漏着陆垫219。在一个备选实施例中,每个半导体本体205的源区216和漏区217保持互相电隔离,没有形成共同源着陆垫或漏着陆垫。
位于源区216和漏区217之间的半导体器件205的部分确定多沟道非平面晶体管200的一个沟道区,并被栅电极213环绕。在本发明的一个实施例中,沟道区是纯的或者未掺杂的单晶硅。在本发明的一个实施例中,沟道区是掺杂的单晶硅。在沟道区掺杂的情况下,通常掺杂的电导率级别在每立方厘米1×1016到1×1019个原子之间。在本发明的一个实施例中,在沟道区掺杂的情况下,通常掺杂成与源区216和漏区217相反的电导性类型。例如,当源区和漏区是n型电导性时,沟道区就会掺杂p型电导性。类似地,当源区和漏区是p型电导性时,沟道区就会是n型电导性。以这种方式,多沟道非平面晶体管200可分别形成NMOS晶体管或PMOS晶体管。
如图2A所示,多沟道非平面晶体管200封装在绝缘介质中,或者层间电介质(ILD)222中。在本发明的一个实施例中,ILD是低介电常数的材料,如多孔的膜层或掺氮的氧化物膜层。在本发明的一个实施例中,ILD由PSG、BPSG、二氧化硅、氮化硅或这些的组合或其它的公知的材料形成。
如图2A所示,多沟道非平面晶体管200通过具有矩接触结构223和226的ILD222电耦合到外部器件。接触结构可以由任何公知的导电材料形成,例如但不限于铝、金、钛、钨、银和碳纳米管。在本发明的一个实施例中,金属接触结构223和226是铜的。在本发明的一个实施例中,金属接触结构223和226具有附加的阻挡层,例如但不限于钽,氮化钽,钛,氮化钛。
应该明白,矩形块接触结构223和226可互相独立地定尺寸(dimensioned)。还应该明白,描述一个块接触结构的结构,如源接触结构223,可独立地应用到漏接触结构226的结构。因此,各种实施例中描述的或图2A到2D中所示的结构可按任何组合来用于源接触或漏接触。
在本发明的一个实施例中,如图2A所示,一个金属源接触结构223与源区216接触,一个金属漏接触结构226与多个半导体本体205的漏区217接触。在本发明的一个实施例中,金属源接触结构223的宽度224约等于半导体本体205的数目乘以晶体管的半导体本体205的间距,长度225约等于最小光刻部件尺寸。在本发明的一个实施例中,金属漏接触结构226的宽度约等于半导体本体205的数目乘以晶体管的半导体本体205的间距,长度约等于最小光刻部件尺寸。在本发明的另一个实施例中,源接触结构223的宽度224远大于长度225,而漏接触结构226的宽度约等于最小光刻尺寸。同样,漏接触结构226也可定成这样尺寸的块接触:宽度远大于长度,而源接触结构有最小光刻尺寸。在本发明的实施例中,考虑到容许一定的偏差,接触结构223的长度225可能比最小光刻尺寸大。
在本发明的一个实施例中,源接触结构223连接到共同源轨道或源着陆垫218,如图2A所示。在本发明的一个实施例中,金属漏接触结构226接触多沟道非平面晶体管200的共同漏轨道或漏着陆垫219。
通过以所述方式确定单个接触结构的尺寸,用于确定金属块接触结构位置的最小光刻间距已不再制约器件的设计,即使当半导体本体205的最小间距是亚光刻尺寸的时也是如此。此外,由于金属块接触结构宽度224变得远大于长度225,块接触结构223开始近似为一维插槽。由于改进的一维成像方法,这样的一维插槽的光刻确定长度225小于二维接触结构(宽度224约等于长度225)的长度。
在本发明的一个实施例中,如图2B所示,多源接触结构223和227与共同源着陆垫218接触,多个漏接触结构226和230与共同漏着陆垫219接触。在本发明的另一个实施例中,源接触结构与没有共同源着陆垫的多个源区接触,漏接触结构与没有共同漏着陆垫的多个漏区接触。在本发明的一个实施例中,块接触结构的宽度224远大于长度225,如图2B所示。在本发明的一个实施例中,接触结构223的宽度224不同于接触结构227的宽度228。在本发明的一个实施例中,接触结构223的长度225不同于接触结构227的长度229。
在本发明的一个实施例中,单个金属源接触结构223以自对准的方式直接接触到没有共同源着陆垫的多个源区216,而漏接触结构226通过漏着陆垫219接触到漏区217,如图2C所示。以类似的方式,金属漏接触结构直接接触到没有共同漏着陆垫的多个漏区。以这种方式,非平面器件的台阶(step)高度增加了金属源接触的有效表面积,因为金属接触结构包围了非平面源区216和非平面漏区217。正如非平面晶体管具有增加的沟道宽度,非平面接触也会有相对于线性接触来说增大的接触宽度,从而降低了接触电阻,并且降低了并联装置的总寄生电阻。
在本发明的某些实施例中,如图2D所示的多沟道非平面晶体管使用接触源区216或源着陆垫218的多个金属源接触结构223和227来电耦合到外部设备。在本发明的另一个实施例中,多个金属漏接触结构以相似的方式与漏区217接触。在本发明的一个实施例中,金属源接触结构223和227中的至少一个结构的宽度224大于半导体本体的间距但小于半导体本体的数目乘以半导体本体的间距,长度225与最小光刻部件尺寸相当。在本发明的另一些实施例中,金属漏接触结构226的至少一个的宽度大于半导体本体的间距但小于半导体本体的数目乘以半导体本体的间距,长度大约是最小光刻部件尺寸,并且接触漏区217或漏着陆垫219。
在本发明的一个实施例中,多个源接触结构223和227与源区216接触,单个金属漏接触结构226与漏区217或着陆垫219接触,如图2D所示。在本发明的某些实施例中,单个金属源接触结构与源区接触而多个漏接触结构与半导体本体的漏区接触。在本发明的一个实施例中,单个源接触结构与共同源着陆垫接触而多个漏接触结构与多个漏区接触。以此方式,在一个并行设备内可实现基本的扇出、加法器或其它逻辑运算,并且可利用如前所述的通过使用具有亚光刻间距的晶体管提供的高布局效率的优越性。因为半导体本体具有亚光刻间距,所以不是所有的半导体本体都必须被本发明的这个实施例中的接触结构223和227接触。然而,因为半导体本体并行运行,所以如果被结构223和227接触的半导体本体获得了足够的电流,那么某些半导体本体的接触失败不一定会影响到整个器件的运行。
图3A到3L图解说明了根据本发明的一个实施例的一种制作三栅极晶体管的方法。非平面晶体管的制作始于衬底302。如图3A所示,硅或半导体膜层在衬底302上形成。在本发明的一个实施例中,衬底302是绝缘衬底,例如图3A中所示。在本发明的一个实施例中,绝缘衬底302包括低单晶硅衬底301和绝缘层303,如二氧化硅膜层或氮化硅膜层。绝缘层303将半导体膜层304与衬底302隔离,并在实施例中形成了200-2000的厚度。绝缘层303有时被称为“埋氧”层。当硅或半导体膜层304在绝缘衬底301上形成时,绝缘衬底300上的硅或半导体(SOI)就产生了。在本发明的另一些实施例中,衬底302可以是“大块”半导体衬底,例如但不限于单晶硅衬底和砷化镓衬底。在用到了“大块”半导体衬底的本发明的一个实施例中,半导体膜层304只是半导体衬底的上部区域。因此,应该明白涉及半导体膜层304的实施例也适用于使用“大块”衬底的“大块”器件的实施例。在本发明的某些实施例中,衬底302是具有掺杂外延层的硅半导体衬底,具有p型或者n型传导性,浓度在每立方厘米1×1016到1×1019个原子之间。
虽然的半导体膜层304是硅膜层,但是在另一些实施例中,它可以是其它的半导体膜层,例如但不限于锗(Ge)、硅锗合金(SixGey)、砷化镓(GaAs)、InSb、GaP、GaSb、InP以及碳纳米管。在本发明的一个实施例中,半导体膜层304是纯(即未掺杂的)硅膜层。在另一些实施例中,半导体膜层304被掺杂成p型或n型导电性,密度在每立方厘米1×1016到1×1019个原子之间。半导体膜层304可原位(insitu)掺杂(即在它淀积的时候掺杂)或在它形成于衬底302以后通过例如离子注入掺杂。在形成后掺杂使PMOS和NMOS三栅器件在相同的绝缘衬底上很容易形成。在这一点上,半导体本体的掺杂级别能够决定器件的沟道区的掺杂级别。
在本发明的某些实施例中,半导体膜层304形成的厚度约等于所制作的三栅晶体管后续形成的半导体本体所要求的高度。在本发明的一个实施例中,半导体膜层304的厚度或高度小于30纳米,而且理想地小于20纳米尺度。在本发明的另一个实施例中,所形成的半导体膜层304的厚度约等于所制作的三栅晶体管要求的栅“长度”的三分之一。在本发明的另一个实施例中,半导体膜层304形成大于器件所要求的栅长的厚度。在本发明的某些实施例中,半导体膜层304形成到某个厚度,该厚度使所制作的三栅晶体管能够以对其设计的栅长(Lg)完全耗尽的方式来运行。
半导体膜层304可按任何公知的方式形成于绝缘衬底302上。在绝缘衬底上形成硅的一种方法,被称为植入氧(SIMOX)分离技术。当前用于形成SOI衬底的另一种技术是通常被称为结合SOI的外延硅膜层转移技术。在本发明的某些实施例中,半导体膜层304是“大块”半导体衬底的一部分。
这时,若需要,为了隔离将要在衬底中逐个形成的各种晶体管,隔离区域(未示出)可形成在衬底300中。隔离区域可利用例如公知的光刻和蚀刻技术通过蚀刻三栅晶体管周围的半导体膜层304的部分。若需要,可执行用绝缘膜层如二氧化硅来回填蚀刻区域。
这时,半导体本体可由半导体膜层304用公知的光刻和消减(subtractive)蚀刻技术确定半导体本体而形成。在本发明的某个实施例中,半导体本体具有光刻尺寸和间距。在本发明的某些实施例中,亚光刻制作技术如间隔区,可用于形成具有亚光刻间距的半导体本体,如图3B-3F所示。在一种方法中,第一掩膜层由公知的电介质或金属材料形成。在本发明的一个实施例中,第一掩膜层是氮化物。在本发明的一个实施例中,第一掩膜层是氧化物。在本发明的另一个实施例中,第一掩膜层是多晶硅。如图3B的透视图所示,第一掩膜层可通过使用公知的光刻和蚀刻工艺来确定成一种芯棒结构340。芯棒结构340如图3C横截面视图所示。芯棒340有足够的高度、宽度和间距使随后形成间隔区具有预定的间距和宽度。在本发明的某些实施例中,芯棒结构可通过使用的特定光刻装置来得到可分解的最小光刻间距341和宽度342。在本发明的一个实施例中,芯棒结构用193纳米光刻成型。在本发明的一个实施例中,芯棒结构具有大约110纳米的间距341。在本发明的一个实施例中,采用例如但不限于利用干蚀刻或湿蚀刻工艺的各向同性蚀刻等公知技术,使得用于确定芯棒340的光确定(photodefine)层在尺寸上进一步减小。在本发明的另一个实施例中,在通过各向同性蚀刻工艺成型后,芯棒结构340在尺寸上减小。
在本发明的某些实施例中,第二掩膜层351在芯棒结构上形成,如图3D所示。第二掩膜层材料是一类公知的适于形成具有使之能承受随后用于去除芯棒的方法的性质的间隔区。第二个掩膜层材料的厚度选择成可使随后形成的间隔区具有预定的宽度。在本发明的一个实施例中,第二掩膜层351可以是公的材料,例如但不限于氮化物、氧化物或多晶硅。第二掩膜层351可以是公知的金属材料。公知的淀积第二掩膜层351的技术可用于实现所要求的阶梯覆盖或所需的制作,例如但不限于化学气相淀积(CVD)、等离子体增强化学气相淀积(PECVD)、高密度等离子体(HDP)或原子层淀积(ALD)。
如图3E所示,第二掩膜材料可使用适于第二掩膜材料的公知的各向异性蚀刻技术来形成邻近芯棒340侧壁的间隔区352。
这样,可通过任何一种选择性去除芯棒而不大量改变间隔区352的蚀刻技术来去除芯棒。在本发明的一个实施例中,使用公知的湿化学蚀刻工艺来去除芯棒。在本发明的另一个实施例中,使用公知的等离子蚀刻工艺来去除芯棒。一旦芯棒被去除,具有预定间距353和宽度354的间隔区结构352保持,如图3F的截面图所示。在本发明的一个实施例中,间隔区结构352的间距353是亚光刻的。在本发明的一个实施例中,间隔区结构间距353大约是芯棒结构间距的一半。在本发明的一个实施例中,间隔区结构352的间距大约在55纳米左右。如图3G的透视图所示,间隔区结构352形成一个图案或多个图案,所述图案确定在半导体膜层304中随后形成半导体本体或散热片(fin)的位置。间隔区352的图案确定随后形成的三栅晶体管的半导体本体或散热片所要求的宽度354。在本发明的一个实施例中,间隔区结构352的宽度353小于或等于30纳米尺度,理想的是小于或等于20纳米尺度。正如本领域的技术人员应该明白的那样,间隔区结构352的形成过程是可重复进行的,每次会使间隔区结构352的数目加倍,而潜在地降低间隔区的间距353和间隔区的宽度354。
这时,若需要,为了在衬底300上形成三栅晶体管,光确定掩膜(未示出)可用于增大间隔区结构352,有选择地保护半导体膜层304没有受到间隔区结构352保护的部分。光刻胶掩膜还可以确定源着陆垫和漏着陆垫。着陆垫可用于将各种源区连接在一起以及将所制作的晶体管的各种漏区连接在一起。在本发明的某些实施例中,光刻胶掩膜还用于确定具有光刻间距的其它半导体本体。光刻胶掩膜可通过公知的光刻技术形成,包括掩蔽(masking)、暴露和形成均厚淀积光刻胶膜。形成光刻胶掩膜后,半导体膜层305蚀刻成与光刻胶掩膜和间隔区结构352对准,以分别形成一个或多个硅结构或散热片和源着陆垫或漏着陆垫318和319,如图3H所示。在本发明的某些实施例中,图3G中的半导体膜层304直到底下的埋氧层303暴露时才被蚀刻。在用到“大块”衬底的本发明的实施例中,半导体膜层304被蚀刻到理想的深度。公知的半导体蚀刻技术,如各向异性等离子蚀刻或反应性离子蚀刻可用于确定如图3H所示的半导体本体305。这时,可以用公知的技术去除间隔区结构352和光刻胶。这时,半导体本体305具有光刻间距的实施例和半导体本体305具有亚光刻的间距的实施例都可以用图3H来表示。
接着,如图3I所示,栅绝缘层在每个半导体305上以依赖于非平面器件的类型(双栅、三栅、ω栅、碳纳米尺度管)的方式来形成。在本发明的一个实施例中,栅绝缘层312是在每个半导体本体305的上表面和每个半导体本体305的横向相反侧壁上形成的。栅绝缘层可以是淀积的电介质或生长的电介质。在本发明的一个实施例中,栅绝缘层312是用干、湿氧化工艺生长的二氧化硅绝缘膜层。在本发明的一个实施例中,二氧化硅的厚度增长到5-15。在本发明的一个实施例中,栅绝缘层312是淀积电介质,例如但不限于高介电常数膜层,如氧化钽、氧化钛、氧化铪、氧化锆、氧化铝或其它高K电介质,如钛酸锶钡(BST)。高介电常数膜层可通过公知的技术形成,如采用化学气相淀积(CVD)和原子层淀积(ALD)。在本发明的一个实施例中,栅绝缘层可由这样的膜层的复合材料组成。
然后,如图3I所示,形成了栅电极313。栅电极313在形成于每个半导体本体305的上表面的栅绝缘层312上形成,在形成于每个半导体本体305的侧壁上或邻近地方的栅绝缘层312上或邻近的地方形成。栅电极可形成的厚度达到200-3000之间。在一个实施例中,栅电极的厚度是半导体本体305高度的至少3倍。在本发明的实施例中,栅电极材料包含多晶硅。在本发明另一的实施例中,栅电极材料包含多晶硅锗合金。在本发明的再一实施例中,栅电极材料还可包含金属膜层,如镍、钴、钨、钛、钽、氮化物和硅化物。在本发明的进一步实施例中,栅电极可以是碳纳米管。栅电极313可由公知的技术形成,如在衬底上均厚淀积栅电极材料然后用公知的光刻和蚀刻技术将栅电极材料成型。在本发明的某些实施例中,用于确定栅电极313的光刻过程使用用于制作非平面晶体管的最低或最小尺寸的光刻工艺。在本发明的一个实施例中,类似于为确定半导体本体305而描述的那个芯棒类型工艺或公知的氧化技术,可被用于形成具有亚光刻尺寸的栅电极313。在本发明的另一些实施例中,“替换栅(replacement gate)”方法用于形成栅电极313。
然后,晶体管的源区316和漏区317在半导体本体305中于栅电极313的相反面上形成,如图3I所示。在本发明的一个实施例中,源区和漏区包括尖端或源/漏延伸区,可通过在栅极的半导体本体中掺杂来形成。如果使用了源区318和漏区319,它们也会在这时掺杂。对于PMOS三栅晶体管来说,半导体散热片或本体305掺杂了p型电导,密度在每立方厘米1×1020-1×1021个原子之间。对于NMOS三栅晶体管来说,半导体散热片或器件305掺杂了n型电导离子,掺杂浓度在每立方厘米1×1020至1×1021个原子之间。在本发明的一个实施例中,硅膜层通过离子注入掺杂。在本发明的另一个实施例中,离子注入出现在垂直方向。当栅电极313是多晶硅电极时,它可以在离子注入的过程中掺杂。栅电极313用作以掩膜防止离子注入步骤掺杂三栅晶体管的沟道区。沟道区是硅本体305位于栅电极313下或周围的一部分。如果栅电极313是金属电极,绝缘硬掩膜可用于在离子注入的过程中阻止掺杂。在另一些实施例中,其它方法,如固态源扩散,可用于掺杂半导体本体以形成源延伸和漏延伸区域。在本发明的实施例中,在源、漏区或源、漏延伸区形成之前,“晕(halo)”区在硅体里形成。
然后,若需要,衬底可经进一步处理以形成更多的附加部件,如重掺杂源/漏接触区域,在源或漏区及栅电极上淀积硅或硅锗,以及在源接触区域/漏接触区域及在栅电极上形成硅化物。在本发明的实施例中,电介质侧壁间隔区可在栅电极的侧壁上形成。侧壁间隔区可用于补偿重源/漏接触注入,在有选择的硅或硅锗淀积、生长过程中隔离源/漏区与栅电极,以及用于在源区和漏区以及栅电极上形成硅化物或锗化物。在本发明的某些实施例中,实现了全面硅化过程(FUSI)。
然后,器件用绝缘层或中间介质层(ILD)322封装,如图3J所示,它们有足够的厚度来隔离器件。在本发明的某些实施例中,ILD 322由公知的材料构成如磷硅玻璃(PSG)、硼磷硅玻璃(BPSG)、正硅酸乙酯(TEOS)、二氧化硅、氮化硅或这些材料的复合。在本发明的一个实施例中,ILD 322是介电常数比二氧化硅低的材料,例如但不限于多孔电介质材料或掺杂碳的硅酸盐电介质材料。ILD可通过公知的工艺来覆盖淀积,例如但不限于低气压化学气相淀积(LPCVD)、PECVD和HDP。
然后,ILD 322被成型和蚀刻,以对金属接触结构360和363确定开口的位置,如图3K所示。在本发明的某些实施例中,用于确定接触开口360和363的光刻工艺具有大于半导体305的间距的最小光刻间距。在本发明的一个实施例中,用于确定接触开口360和363的光刻工艺是193纳米。在本发明的一个实施例中,所形成的接触开口360和363具有宽度尺寸361和长度362,宽度361约等于半导体本体305的数目乘以半导体本体305的间距,长度362约等于最小光刻部件尺寸。在本发明的一个实施例中,接触开口360和363具有宽度361和长度362,宽度361大于半导体本体305的间距但小于半导体305的数目乘以半导体的间距,长度362大约是最小光刻部件尺寸。在本发明的某些实施例中,接触开口360和363的宽度361远大于长度362。在本发明的某些实施例中,接触开口360和363可被想象成“一维”插槽,其长度362小于接触开口是二维(宽度大约和长度一样大)时可能的长度。在本发明的另一些实施例中,接触结构360和363的维数是不相等的。
在本发明的一个实施例中,接触开口360和363分别终止于源着陆垫318或漏着陆垫319。在本发明的另一个没有源着陆垫或漏着陆垫的实施例中,接触开口360和363分别设置成暴露多个源区316和多个漏区317。在本发明的某些实施例中,接触开口采用公知的各向异性等离子或反应性离子蚀刻工艺蚀刻到ILD 322中,这些工艺对半导体源区316和漏区317具有足够的选择性,使得ILD 322被完全去除以暴露非平面源区316和非平面漏区317(或着陆垫318和319)。
然后,用金属填充接触开口360,以形成金属接触结构323和326,如图3L所示。接触结构323和326可由公知的导电材料形成,例如但不限于铜、钨、铝、黄金或碳纳米管。接触开口360的填充可通过当前已知的任何技术来实现,例如但不限于物理气相淀积(PVD)、CVD、ALD、化学镀或电解镀或这些技术的组合。若需要,填充接触开口360的方法可包括公知的阻挡层的淀积,例如但不限于钽或钽氮化物或其它金属间化合物。若需要,填充接触开口360的方法可包括公知的籽晶层的淀积,例如但不限于铜、钛或其它金属间化合物。
然后,如图3L所示,用于形成金属接触结构323和326的导电物质用公知的电解、化学、机械去除手段或这些的组合来抛光。在本发明的一个实施例中,在镶嵌或双重镶嵌技术中使用了化学机械抛光(CMP)过程。以此方式,在需要时,导电接触结构323和326可被平坦化以与ILD 322基本水平,随后可与金属的附加层互连。
从而,描述了一种具有多个并行纳米尺度沟道、新颖的接触结构的器件和它的制作方法。

Claims (17)

1.一种器件,包括:
多个并行半导体本体,所述多个并行半导体本体的每一个具有上表面和一对横向相反的侧壁,所述并行半导体本体的每一个具有在源区和漏区之间的沟道部分;
单栅电极,邻近和在所述多个本体的每一个的所述沟道区上形成;
金属源接触,耦合并延伸在所述多个并行本体的每一个的所述源区之间;
金属漏接触,耦合并延伸在所述多个并行本体的每一个的所述漏区之间。
2.如权利要求1所述的器件,其中,所述并行本体具有第一宽度和第一间距,所述第一间距小于光刻工艺确定的间距。
3.如权利要求2所述的器件,其中,所述的光刻工艺使用193纳米光刻技术。
4.如权利要求2所述的器件,其中,所述第一间距小于110纳米。
5.如权利要求2所述的器件,其中,所述间距是由所述光刻工艺确定的所述间距的一半。
6.如权利要求1所述的器件,还包括与所述多个并行本体的所述源区直接接触的源着陆垫,其中,所述源着陆垫由与所述并行本体相同的材料形成,所形成的金属源接触与所述源着陆垫直接接触。
7.如权利要求1所述的器件,还包括与所述多个并行本体的所述漏区直接接触的漏着陆垫,其中,所述漏着陆垫由与所述多个并行本体相同的材料形成,所形成的金属漏接触与所述漏着陆垫直接接触。
8.如权利要求1所述的器件,其中,所述多个并行本体由从硅、锗、卤化硅、GaAs、InSb和碳纳米管组成的组中选出的材料形成。
9.如权利要求8所述的半导体器件,其中,所述多个并行本体在绝缘衬底上形成。
10.一种器件,包括:
多个并行半导体本体,所述多个并行半导体本体的每一个具有上表面和一对横向相反的侧壁,所述并行本体的每一个具有在源区和漏区之间的沟道部分;
单栅电极,邻近和在所述多个本体的每一个的所述沟道区上形成;
第一金属接触和第二金属接触,其中,所述第一金属接触和所述第二金属接触这两者中的至少一个耦合并延伸在所述多个并行本体之间。
11.一种形成半导体器件的方法,包括:
在半导体膜层上形成具有第一间距的多个并行间隔区;
蚀刻与所述多个并行间隔区对准的所述半导体膜层,以形成多个多个并行半导体本体;
邻近和在所述多个并行半导体本体上形成单栅电极;
在所述并行半导体本体的每一个中于所述栅电极的相反面上形成源区和漏区;
形成耦合并延伸在所述半导体本体的所述源区之间的单个金属源接触;以及
形成耦合并延伸在所述多个半导体本体的所述漏区之间的单个金属漏接触。
12.如权利要求11所述的方法,其中,所述多个并行间隔区通过以下方法形成:
形成并行部件的第一图案,与第一材料具有第二间距,其中所述第二间距比所述第一间距;
邻近和在并行部件的所述第一图案上均厚淀积第二材料的共形膜层;以及
各向异性地蚀刻所述共形膜层,以由所述第二材料形成所述多个并行间隔区;以及
去除所述第一材料的并行部件的所述第一图案。
13.如权利要求12所述的方法,其中,并行部件的所述第一图案通过在所述第一材料上形成光刻胶掩膜以及各向异性地蚀刻与所述光刻胶掩膜对准的所述第一材料来形成。
14.如权利要求13所述的方法,其中,所述光刻胶掩膜通过均厚淀积光刻胶膜层并使所述光刻胶膜层形成具有所述第二间距的多个并行部件来形成,所述第二间距是使用光刻工艺在所述光刻胶膜层中可确定的最小间距。
15.一种形成半导体器件的方法,包括:
形成多个并行半导体本体,其中,所述半导体本体的每一个具有在源区和漏区之间沟道区;
邻近和在所述多个并行半导体本体的所述沟道区上形成单栅电极;
在所述栅电极和所述多个并行半导体本体上形成绝缘层;
在所述绝缘层中形成单个漏开口,它暴露所述多个并行半导体本体的所述漏区并在所述漏区之间延伸,及在所述绝缘层中形成单个源开口,它暴露所述半导体本体的所述源区并在所述源区之间延伸;以及
用金属膜层填充所述单个漏区开口和所述单个源区开口,所述金属膜层与所述多个并行半导体本体的所述源区和所述漏区接触。
16.如权利要求15所述的方法,还包括,其中所述金属膜层被均厚淀积在所述源区开口和所述漏区开口中及所述绝缘层的上表面上;以及
从所述绝缘层的上表面抛光所述金属膜层,以形成单个漏接触和单个源接触。
17.如权利要求16所述的方法,其中,所述金属膜层利用无电镀的或电镀淀积工艺在所述开口中形成。
CN200680023301.XA 2005-06-30 2006-06-29 纳米尺度沟道晶体管的块接触结构 Active CN101208805B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/173,866 US7279375B2 (en) 2005-06-30 2005-06-30 Block contact architectures for nanoscale channel transistors
US11/173,866 2005-06-30
PCT/US2006/025751 WO2007005697A2 (en) 2005-06-30 2006-06-29 Block contact architectures for nanoscale channel transistors

Publications (2)

Publication Number Publication Date
CN101208805A true CN101208805A (zh) 2008-06-25
CN101208805B CN101208805B (zh) 2014-07-30

Family

ID=37433903

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200680023301.XA Active CN101208805B (zh) 2005-06-30 2006-06-29 纳米尺度沟道晶体管的块接触结构

Country Status (8)

Country Link
US (2) US7279375B2 (zh)
JP (1) JP2008544558A (zh)
KR (1) KR101021369B1 (zh)
CN (1) CN101208805B (zh)
DE (1) DE112006001735B4 (zh)
GB (1) GB2442379B (zh)
TW (1) TWI314779B (zh)
WO (1) WO2007005697A2 (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103296083A (zh) * 2012-02-27 2013-09-11 中国科学院微电子研究所 半导体场效应晶体管及其制作方法
CN109065611A (zh) * 2011-12-23 2018-12-21 英特尔公司 具有非分立的源极区和漏极区的纳米线结构
CN109148564A (zh) * 2017-06-16 2019-01-04 韩国科学技术研究院 场效应晶体管、生物传感器及其制造方法
CN109427593A (zh) * 2017-08-31 2019-03-05 台湾积体电路制造股份有限公司 制造半导体装置的方法
CN110164969A (zh) * 2018-02-13 2019-08-23 隽佾科技有限公司 波浪式场效晶体管结构
CN110190122A (zh) * 2018-02-23 2019-08-30 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
TWI712120B (zh) * 2018-06-19 2020-12-01 日商松下半導體解決方案股份有限公司 半導體裝置
TWI809539B (zh) * 2021-07-28 2023-07-21 南亞科技股份有限公司 具有不同寬度之導電接觸點的半導體元件結構及其製備方法

Families Citing this family (206)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004068574A1 (de) * 2003-01-30 2004-08-12 X-Fab Semiconductor Foundries Ag Soi kontaktstruktur(en) und zugehöriges herstellungsverfahren
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US6909151B2 (en) 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US7268058B2 (en) * 2004-01-16 2007-09-11 Intel Corporation Tri-gate transistors and methods to fabricate same
US7154118B2 (en) * 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
KR100632475B1 (ko) * 2004-07-26 2006-10-09 삼성전자주식회사 성능이 향상된 멀티 게이트 트랜지스터의 제조 방법 및이에 의해 제조된 멀티 게이트 트랜지스터
KR100545863B1 (ko) * 2004-07-30 2006-01-24 삼성전자주식회사 핀 구조물을 갖는 반도체 장치 및 이를 제조하는 방법
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7422946B2 (en) * 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US7332439B2 (en) * 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US7361958B2 (en) * 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US20060202266A1 (en) * 2005-03-14 2006-09-14 Marko Radosavljevic Field effect transistor with metal source/drain regions
US7858481B2 (en) * 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) * 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7402875B2 (en) * 2005-08-17 2008-07-22 Intel Corporation Lateral undercut of metal gate in SOI device
US7339241B2 (en) * 2005-08-31 2008-03-04 Freescale Semiconductor, Inc. FinFET structure with contacts
US7381655B2 (en) * 2005-09-14 2008-06-03 International Business Machines Corporation Mandrel/trim alignment in SIT processing
US20070090416A1 (en) * 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US7479421B2 (en) * 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US20070090408A1 (en) * 2005-09-29 2007-04-26 Amlan Majumdar Narrow-body multiple-gate FET with dominant body transistor for high performance
US7638381B2 (en) * 2005-10-07 2009-12-29 International Business Machines Corporation Methods for fabricating a semiconductor structure using a mandrel and semiconductor structures formed thereby
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
US8183556B2 (en) * 2005-12-15 2012-05-22 Intel Corporation Extreme high mobility CMOS logic
US7968394B2 (en) 2005-12-16 2011-06-28 Freescale Semiconductor, Inc. Transistor with immersed contacts and methods of forming thereof
US20070152266A1 (en) * 2005-12-29 2007-07-05 Intel Corporation Method and structure for reducing the external resistance of a three-dimensional transistor through use of epitaxial layers
JP2007299991A (ja) * 2006-05-01 2007-11-15 Toshiba Corp 半導体装置及びその製造方法
US7517764B2 (en) * 2006-06-29 2009-04-14 International Business Machines Corporation Bulk FinFET device
US8143646B2 (en) * 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
US7456471B2 (en) * 2006-09-15 2008-11-25 International Business Machines Corporation Field effect transistor with raised source/drain fin straps
KR101225641B1 (ko) * 2006-12-27 2013-01-24 삼성전자주식회사 반도체 소자 및 그 제조 방법
US20080157225A1 (en) * 2006-12-29 2008-07-03 Suman Datta SRAM and logic transistors with variable height multi-gate transistor architecture
US8039870B2 (en) * 2008-01-28 2011-10-18 Rf Nano Corporation Multifinger carbon nanotube field-effect transistor
CN101669196B (zh) 2007-01-30 2013-01-02 射频纳米公司 多指栅碳纳米管场效应晶体管
US20080237672A1 (en) * 2007-03-30 2008-10-02 Doyle Brian S High density memory
US8450165B2 (en) 2007-05-14 2013-05-28 Intel Corporation Semiconductor device having tipless epitaxial source/drain regions
US20080290414A1 (en) * 2007-05-24 2008-11-27 Texas Instruments Incorporated Integrating strain engineering to maximize system-on-a-chip performance
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US7898040B2 (en) * 2007-06-18 2011-03-01 Infineon Technologies Ag Dual gate FinFET
US8134208B2 (en) * 2007-09-26 2012-03-13 Globalfoundries Inc. Semiconductor device having decreased contact resistance
US8043978B2 (en) * 2007-10-11 2011-10-25 Riken Electronic device and method for producing electronic device
US7910994B2 (en) * 2007-10-15 2011-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for source/drain contact processing
ES2489615T3 (es) * 2007-12-11 2014-09-02 Apoteknos Para La Piel, S.L. Uso de un compuesto derivado del acido p-hidroxifenil propionico para el tratamiento de la psoriasis
US7790531B2 (en) 2007-12-18 2010-09-07 Micron Technology, Inc. Methods for isolating portions of a loop of pitch-multiplied material and related structures
JP4591525B2 (ja) * 2008-03-12 2010-12-01 ソニー株式会社 半導体装置
US7833889B2 (en) 2008-03-14 2010-11-16 Intel Corporation Apparatus and methods for improving multi-gate device performance
US8278687B2 (en) * 2008-03-28 2012-10-02 Intel Corporation Semiconductor heterostructures to reduce short channel effects
US8129749B2 (en) * 2008-03-28 2012-03-06 Intel Corporation Double quantum well structures for transistors
US7800166B2 (en) * 2008-05-30 2010-09-21 Intel Corporation Recessed channel array transistor (RCAT) structures and method of formation
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US8076208B2 (en) * 2008-07-03 2011-12-13 Micron Technology, Inc. Method for forming transistor with high breakdown voltage using pitch multiplication technique
US7833891B2 (en) * 2008-07-23 2010-11-16 International Business Machines Corporation Semiconductor device manufacturing method using oxygen diffusion barrier layer between buried oxide layer and high K dielectric layer
US7884354B2 (en) * 2008-07-31 2011-02-08 Intel Corporation Germanium on insulator (GOI) semiconductor substrates
US7781283B2 (en) * 2008-08-15 2010-08-24 International Business Machines Corporation Split-gate DRAM with MuGFET, design structure, and method of manufacture
US7979836B2 (en) * 2008-08-15 2011-07-12 International Business Machines Corporation Split-gate DRAM with MuGFET, design structure, and method of manufacture
KR101104248B1 (ko) * 2008-12-23 2012-01-11 한국전자통신연구원 자기 정렬 전계 효과 트랜지스터 구조체
TWI392093B (zh) * 2009-01-09 2013-04-01 Univ Nat Sun Yat Sen 金屬氧化物半導體裝置及其製造方法
US8222154B2 (en) * 2009-02-10 2012-07-17 International Business Machines Corporation Fin and finFET formation by angled ion implantation
US8305829B2 (en) 2009-02-23 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Memory power gating circuit for controlling internal voltage of a memory array, system and method for controlling the same
US8184472B2 (en) * 2009-03-13 2012-05-22 International Business Machines Corporation Split-gate DRAM with lateral control-gate MuGFET
US8305790B2 (en) 2009-03-16 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical anti-fuse and related applications
US8957482B2 (en) 2009-03-31 2015-02-17 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical fuse and related applications
US7902541B2 (en) * 2009-04-03 2011-03-08 International Business Machines Corporation Semiconductor nanowire with built-in stress
US8912602B2 (en) 2009-04-14 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods for forming the same
US8084308B2 (en) * 2009-05-21 2011-12-27 International Business Machines Corporation Single gate inverter nanowire mesh
US8053318B2 (en) 2009-06-25 2011-11-08 International Business Machines Corporation FET with replacement gate structure and method of fabricating the same
US8461015B2 (en) 2009-07-08 2013-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. STI structure and method of forming bottom void in same
US9484462B2 (en) 2009-09-24 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of fin field effect transistor
US8264032B2 (en) 2009-09-01 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Accumulation type FinFET, circuits and fabrication method thereof
US8298925B2 (en) 2010-11-08 2012-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming ultra shallow junction
US8497528B2 (en) 2010-05-06 2013-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a strained structure
US8629478B2 (en) 2009-07-31 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure for high mobility multiple-gate transistor
US8472227B2 (en) 2010-01-27 2013-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits and methods for forming the same
US8440517B2 (en) 2010-10-13 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of fabricating the same
US8980719B2 (en) 2010-04-28 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for doping fin field-effect transistors
US8623728B2 (en) 2009-07-28 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming high germanium concentration SiGe stressor
US8482073B2 (en) * 2010-03-25 2013-07-09 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit including FINFETs and methods for forming the same
US8187928B2 (en) 2010-09-21 2012-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuits
US8264021B2 (en) 2009-10-01 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Finfets and methods for forming the same
US8759943B2 (en) 2010-10-08 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor having notched fin structure and method of making the same
JP4922373B2 (ja) * 2009-09-16 2012-04-25 株式会社東芝 半導体装置およびその製造方法
US8946028B2 (en) * 2009-10-06 2015-02-03 International Business Machines Corporation Merged FinFETs and method of manufacturing the same
US8097515B2 (en) * 2009-12-04 2012-01-17 International Business Machines Corporation Self-aligned contacts for nanowire field effect transistors
US8173993B2 (en) * 2009-12-04 2012-05-08 International Business Machines Corporation Gate-all-around nanowire tunnel field effect transistors
US8143113B2 (en) * 2009-12-04 2012-03-27 International Business Machines Corporation Omega shaped nanowire tunnel field effect transistors fabrication
US8129247B2 (en) 2009-12-04 2012-03-06 International Business Machines Corporation Omega shaped nanowire field effect transistors
US8384065B2 (en) * 2009-12-04 2013-02-26 International Business Machines Corporation Gate-all-around nanowire field effect transistors
US8455334B2 (en) * 2009-12-04 2013-06-04 International Business Machines Corporation Planar and nanowire field effect transistors
US8440998B2 (en) * 2009-12-21 2013-05-14 Intel Corporation Increasing carrier injection velocity for integrated circuit devices
US20110147840A1 (en) * 2009-12-23 2011-06-23 Cea Stephen M Wrap-around contacts for finfet and tri-gate devices
US8633470B2 (en) * 2009-12-23 2014-01-21 Intel Corporation Techniques and configurations to impart strain to integrated circuit devices
US8722492B2 (en) * 2010-01-08 2014-05-13 International Business Machines Corporation Nanowire pin tunnel field effect devices
US9040393B2 (en) 2010-01-14 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor structure
KR20190038687A (ko) 2010-02-05 2019-04-08 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치, 및 반도체 장치의 제조 방법
US8310013B2 (en) * 2010-02-11 2012-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a FinFET device
US8399931B2 (en) 2010-06-30 2013-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Layout for multiple-fin SRAM cell
US8324940B2 (en) 2010-04-13 2012-12-04 International Business Machines Corporation Nanowire circuits in matched devices
US8361907B2 (en) 2010-05-10 2013-01-29 International Business Machines Corporation Directionally etched nanowire field effect transistors
US8324030B2 (en) 2010-05-12 2012-12-04 International Business Machines Corporation Nanowire tunnel field effect transistors
US8513099B2 (en) * 2010-06-17 2013-08-20 International Business Machines Corporation Epitaxial source/drain contacts self-aligned to gates for deposited FET channels
US8298881B2 (en) * 2010-06-28 2012-10-30 International Business Machines Corporation Nanowire FET with trapezoid gate structure
US9029834B2 (en) * 2010-07-06 2015-05-12 International Business Machines Corporation Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric
US8835231B2 (en) 2010-08-16 2014-09-16 International Business Machines Corporation Methods of forming contacts for nanowire field effect transistors
US8268689B2 (en) * 2010-08-23 2012-09-18 International Business Machines Corporation Multiple threshold voltages in field effect transistor devices
US8536563B2 (en) 2010-09-17 2013-09-17 International Business Machines Corporation Nanowire field effect transistors
JP5654818B2 (ja) 2010-09-27 2015-01-14 ルネサスエレクトロニクス株式会社 パワー系半導体装置の製造方法
US8603924B2 (en) 2010-10-19 2013-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming gate dielectric material
US9048181B2 (en) 2010-11-08 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming ultra shallow junction
US8769446B2 (en) 2010-11-12 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method and device for increasing fin device density for unaligned fins
US8901537B2 (en) * 2010-12-21 2014-12-02 Intel Corporation Transistors with high concentration of boron doped germanium
US8877602B2 (en) 2011-01-25 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms of doping oxide for forming shallow trench isolation
US8592915B2 (en) 2011-01-25 2013-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Doped oxide for shallow trench isolation (STI)
US8753964B2 (en) * 2011-01-27 2014-06-17 International Business Machines Corporation FinFET structure having fully silicided fin
KR101140010B1 (ko) * 2011-02-28 2012-06-14 에스케이하이닉스 주식회사 반도체 소자 및 그 형성방법
US8431453B2 (en) 2011-03-31 2013-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure
FR2973570A1 (fr) * 2011-04-01 2012-10-05 St Microelectronics Sa Transistor a tension d'alimentation et/ou de seuil ajustables
US8728892B2 (en) * 2011-05-05 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. Adaptive fin design for FinFETs
US8785911B2 (en) * 2011-06-23 2014-07-22 International Business Machines Corporation Graphene or carbon nanotube devices with localized bottom gates and gate dielectric
US8969154B2 (en) * 2011-08-23 2015-03-03 Micron Technology, Inc. Methods for fabricating semiconductor device structures and arrays of vertical transistor devices
US9287385B2 (en) 2011-09-01 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-fin device and method of making same
KR101605643B1 (ko) * 2011-09-29 2016-03-22 인텔 코포레이션 반도체 응용을 위한 양전성 금속 포함 층을 포함하는 장치 및 그 제조방법
JP5562921B2 (ja) * 2011-10-21 2014-07-30 株式会社東芝 半導体装置
US8693235B2 (en) 2011-12-06 2014-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for finFET SRAM arrays in integrated circuits
US8664729B2 (en) * 2011-12-14 2014-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for reduced gate resistance finFET
KR101631778B1 (ko) 2011-12-23 2016-06-24 인텔 코포레이션 랩-어라운드 컨택트들을 가진 나노와이어 구조들
CN104160511B (zh) * 2011-12-30 2017-06-23 英特尔公司 环绕式沟槽接触部结构和制作方法
US20130221414A1 (en) * 2012-02-27 2013-08-29 Chao Zhao Semiconductor FET and Method for Manufacturing the Same
US20130240997A1 (en) * 2012-03-19 2013-09-19 International Business Machines Corporation Contact bars for modifying stress in semiconductor device and related method
US8927432B2 (en) * 2012-06-14 2015-01-06 International Business Machines Corporation Continuously scalable width and height semiconductor fins
US9093556B2 (en) 2012-08-21 2015-07-28 Stmicroelectronics, Inc. Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods
US9064745B2 (en) * 2012-08-29 2015-06-23 International Business Machines Corporation Sublithographic width finFET employing solid phase epitaxy
US9041106B2 (en) * 2012-09-27 2015-05-26 Intel Corporation Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates
US20140106529A1 (en) * 2012-10-16 2014-04-17 Stmicroelectronics (Crolles 2) Sas Finfet device with silicided source-drain regions and method of making same using a two step anneal
NL2009833C2 (nl) * 2012-11-16 2014-05-19 People Creating Value Holding B V Inrichting voor het bereiden van een drank alsmede een zetinrichting.
KR101983633B1 (ko) 2012-11-30 2019-05-29 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US9397217B2 (en) * 2012-12-28 2016-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of non-planar semiconductor device
US9224849B2 (en) * 2012-12-28 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Transistors with wrapped-around gates and methods for forming the same
KR102049774B1 (ko) * 2013-01-24 2019-11-28 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US9123654B2 (en) * 2013-02-15 2015-09-01 International Business Machines Corporation Trilayer SIT process with transfer layer for FINFET patterning
US9653615B2 (en) 2013-03-13 2017-05-16 International Business Machines Corporation Hybrid ETSOI structure to minimize noise coupling from TSV
CN103219384B (zh) * 2013-04-03 2015-05-20 北京大学 一种抗单粒子辐射的多栅器件及其制备方法
US9111801B2 (en) * 2013-04-04 2015-08-18 Stmicroelectronics, Inc. Integrated circuit devices and fabrication techniques
TWI575564B (zh) * 2013-04-10 2017-03-21 聯華電子股份有限公司 半導體結構製作方法
US9337261B2 (en) * 2013-04-10 2016-05-10 GlobalFoundries, Inc. Method of forming microelectronic or micromechanical structures
US9006842B2 (en) 2013-05-30 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Tuning strain in semiconductor devices
US20150001630A1 (en) * 2013-06-27 2015-01-01 GlobalFoundries, Inc. Structure and methods of fabricating y-shaped dmos finfet
US9349850B2 (en) 2013-07-17 2016-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Thermally tuning strain in semiconductor devices
KR102068980B1 (ko) 2013-08-01 2020-01-22 삼성전자 주식회사 반도체 장치 및 그 제조 방법
DE102014220672A1 (de) 2013-10-22 2015-05-07 Semiconductor Energy Laboratory Co., Ltd. Halbleitervorrichtung
KR101897569B1 (ko) * 2013-12-04 2018-09-13 코웨이 주식회사 커피추출장치
EP3084815A4 (en) * 2013-12-19 2018-01-03 Intel Corporation Self-aligned gate edge and local interconnect and method to fabricate same
EP2887399B1 (en) * 2013-12-20 2017-08-30 Imec A method for manufacturing a transistor device and associated device
US20150194433A1 (en) * 2014-01-08 2015-07-09 Broadcom Corporation Gate substantial contact based one-time programmable device
KR102224525B1 (ko) 2014-02-03 2021-03-08 삼성전자주식회사 레이아웃 디자인 시스템, 이를 이용하여 제조한 반도체 장치 및 그 반도체 장치의 제조 방법
US9397101B2 (en) * 2014-03-06 2016-07-19 Qualcomm Incorporated Stacked common gate finFET devices for area optimization
US9171934B2 (en) * 2014-04-01 2015-10-27 Globalfoundries Inc. Methods of forming semiconductor devices using a layer of material having a plurality of trenches formed therein
US9299781B2 (en) 2014-04-01 2016-03-29 Globalfoundries Inc. Semiconductor devices with contact structures and a gate structure positioned in trenches formed in a layer of material
US9590105B2 (en) * 2014-04-07 2017-03-07 National Chiao-Tung University Semiconductor device with metal alloy over fin, conductive layer over channel region of fin, and semiconductive layer over conductive layer and formation thereof
US9466669B2 (en) * 2014-05-05 2016-10-11 Samsung Electronics Co., Ltd. Multiple channel length finFETs with same physical gate length
JP6537341B2 (ja) * 2014-05-07 2019-07-03 株式会社半導体エネルギー研究所 半導体装置
EP3140862B1 (en) 2014-05-08 2020-11-11 Intel Corporation Necked interconnect fuse structure for integrated circuits
CN105097535B (zh) * 2014-05-12 2018-03-13 中国科学院微电子研究所 FinFet器件的制造方法
US10164115B2 (en) 2014-06-27 2018-12-25 Intel Corporation Non-linear fin-based devices
US9917240B2 (en) 2014-07-24 2018-03-13 Samsung Electronics Co., Ltd. Thermoelectric element, method of manufacturing the same and semiconductor device including the same
US9466731B2 (en) * 2014-08-12 2016-10-11 Empire Technology Development Llc Dual channel memory
US9985026B2 (en) 2014-08-15 2018-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor, integrated circuit and method of fabricating the same
US9893159B2 (en) 2014-08-15 2018-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor, integrated circuit and method of fabricating the same
JP6373686B2 (ja) * 2014-08-22 2018-08-15 ルネサスエレクトロニクス株式会社 半導体装置
KR102230198B1 (ko) 2014-09-23 2021-03-19 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US9362285B2 (en) * 2014-10-02 2016-06-07 International Business Machines Corporation Structure and method to increase contact area in unmerged EPI integration for CMOS FinFETs
TWI678768B (zh) 2014-11-20 2019-12-01 日商新力股份有限公司 半導體裝置
KR102174144B1 (ko) * 2014-12-03 2020-11-04 삼성전자주식회사 반도체 장치 및 그 제조 방법
US20160163646A1 (en) * 2014-12-05 2016-06-09 Qualcomm Incorporated Strapped contact in a semiconductor device
TWI641135B (zh) * 2014-12-12 2018-11-11 聯華電子股份有限公司 具有磊晶結構之鰭狀場效電晶體
US9472574B2 (en) * 2015-01-29 2016-10-18 Globalfoundries Inc. Ultrathin body (UTB) FinFET semiconductor structure
KR102301503B1 (ko) * 2015-02-02 2021-09-13 삼성디스플레이 주식회사 폴더블 표시 장치
KR102310080B1 (ko) 2015-03-02 2021-10-12 삼성전자주식회사 반도체 장치 및 반도체 장치의 제조 방법
KR102407994B1 (ko) * 2015-03-23 2022-06-14 삼성전자주식회사 반도체 소자 및 이의 제조 방법
KR102251060B1 (ko) 2015-04-06 2021-05-14 삼성전자주식회사 반도체 장치 및 반도체 장치의 제조 방법
US9941157B2 (en) * 2015-06-26 2018-04-10 Taiwan Semiconductor Manufacturing Company, Ltd. Porogen bonded gap filling material in semiconductor manufacturing
WO2017052562A1 (en) 2015-09-24 2017-03-30 Intel Corporation Methods of forming backside self-aligned vias and structures formed thereby
CN108028280B (zh) * 2015-09-25 2023-04-04 英特尔公司 制作背侧金属的接触部的卷绕源极/漏极方法
US9449986B1 (en) 2015-10-13 2016-09-20 Samsung Electronics Co., Ltd. 3-dimensional memory device having peripheral circuit devices having source/drain contacts with different spacings
US10026662B2 (en) * 2015-11-06 2018-07-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and fabricating method thereof
KR102415328B1 (ko) 2015-12-03 2022-06-30 삼성전자주식회사 전기적 특성을 개선할 수 있는 에스램 소자 및 이를 포함하는 로직 소자
US9679965B1 (en) 2015-12-07 2017-06-13 Samsung Electronics Co., Ltd. Semiconductor device having a gate all around structure and a method for fabricating the same
US9899490B2 (en) * 2016-02-03 2018-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with changeable gate length and method for forming the same
WO2017145906A1 (ja) * 2016-02-25 2017-08-31 株式会社ソシオネクスト 半導体集積回路装置
WO2017171842A1 (en) 2016-04-01 2017-10-05 Intel Corporation Transistor cells including a deep via lined with a dielectric material
US9755073B1 (en) * 2016-05-11 2017-09-05 International Business Machines Corporation Fabrication of vertical field effect transistor structure with strained channels
US9905663B2 (en) 2016-06-24 2018-02-27 International Business Machines Corporation Fabrication of a vertical fin field effect transistor with a reduced contact resistance
US10283590B2 (en) * 2016-07-06 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Field-effect transistors having contacts to 2D material active region
BR112019001313A2 (pt) 2016-08-26 2019-04-30 Intel Corporation estruturas de dispositivo de circuito integrado e técnicas de fabricação de frente e verso
TWI624064B (zh) * 2016-08-29 2018-05-11 雋佾科技有限公司 波浪式場效電晶體結構
US10516047B2 (en) * 2016-11-28 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device structure
US11139241B2 (en) 2016-12-07 2021-10-05 Intel Corporation Integrated circuit device with crenellated metal trace layout
CN108257968A (zh) * 2016-12-28 2018-07-06 上海新昇半导体科技有限公司 一种无结半导体沟道栅阵列存储器结构及其制备方法
KR102365109B1 (ko) 2017-08-22 2022-02-18 삼성전자주식회사 집적회로 장치
WO2019132863A1 (en) 2017-12-26 2019-07-04 Intel Corporation Stacked transistors with contact last
US20190267491A1 (en) * 2018-02-27 2019-08-29 Bruckewell Technology Corp., Ltd. Wavy fet structure
WO2019172879A1 (en) 2018-03-05 2019-09-12 Intel Corporation Metallization structures for stacked device connectivity and their methods of fabrication
US10790271B2 (en) * 2018-04-17 2020-09-29 International Business Machines Corporation Perpendicular stacked field-effect transistor device
US11688780B2 (en) 2019-03-22 2023-06-27 Intel Corporation Deep source and drain for transistor structures with back-side contact metallization

Family Cites Families (421)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4231149A (en) 1978-10-10 1980-11-04 Texas Instruments Incorporated Narrow band-gap semiconductor CCD imaging device and method of fabrication
GB2156149A (en) 1984-03-14 1985-10-02 Philips Electronic Associated Dielectrically-isolated integrated circuit manufacture
US4487652A (en) 1984-03-30 1984-12-11 Motorola, Inc. Slope etch of polyimide
US4711701A (en) 1986-09-16 1987-12-08 Texas Instruments Incorporated Self-aligned transistor method
US5514885A (en) 1986-10-09 1996-05-07 Myrick; James J. SOI methods and apparatus
US4818715A (en) 1987-07-09 1989-04-04 Industrial Technology Research Institute Method of fabricating a LDDFET with self-aligned silicide
US4907048A (en) 1987-11-23 1990-03-06 Xerox Corporation Double implanted LDD transistor self-aligned with gate
US4905063A (en) 1988-06-21 1990-02-27 American Telephone And Telegraph Company, At&T Bell Laboratories Floating gate memories
JPH0214578A (ja) 1988-07-01 1990-01-18 Fujitsu Ltd 半導体装置
KR910010043B1 (ko) 1988-07-28 1991-12-10 한국전기통신공사 스페이서를 이용한 미세선폭 형성방법
US4994873A (en) 1988-10-17 1991-02-19 Motorola, Inc. Local interconnect for stacked polysilicon device
US5346834A (en) * 1988-11-21 1994-09-13 Hitachi, Ltd. Method for manufacturing a semiconductor device and a semiconductor memory device
US4906589A (en) * 1989-02-06 1990-03-06 Industrial Technology Research Institute Inverse-T LDDFET with self-aligned silicide
JPH02302044A (ja) 1989-05-16 1990-12-14 Fujitsu Ltd 半導体装置の製造方法
US5328810A (en) * 1990-05-07 1994-07-12 Micron Technology, Inc. Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process
KR930003790B1 (ko) * 1990-07-02 1993-05-10 삼성전자 주식회사 반도체 장치의 캐패시터용 유전체
US5278102A (en) 1990-08-18 1994-01-11 Fujitsu Limited SOI device and a fabrication process thereof
JP3061406B2 (ja) 1990-09-28 2000-07-10 株式会社東芝 半導体装置
JP3202223B2 (ja) * 1990-11-27 2001-08-27 日本電気株式会社 トランジスタの製造方法
US5521859A (en) 1991-03-20 1996-05-28 Fujitsu Limited Semiconductor memory device having thin film transistor and method of producing the same
DE69213539T2 (de) 1991-04-26 1997-02-20 Canon Kk Halbleitervorrichtung mit verbessertem isoliertem Gate-Transistor
JPH05152293A (ja) 1991-04-30 1993-06-18 Sgs Thomson Microelectron Inc 段差付き壁相互接続体及びゲートの製造方法
US5346836A (en) 1991-06-06 1994-09-13 Micron Technology, Inc. Process for forming low resistance contacts between silicide areas and upper level polysilicon interconnects
US5292670A (en) * 1991-06-10 1994-03-08 Texas Instruments Incorporated Sidewall doping technique for SOI transistors
US5179037A (en) 1991-12-24 1993-01-12 Texas Instruments Incorporated Integration of lateral and vertical quantum well transistors in the same epitaxial stack
US5391506A (en) * 1992-01-31 1995-02-21 Kawasaki Steel Corporation Manufacturing method for semiconductor devices with source/drain formed in substrate projection.
JPH05243572A (ja) 1992-02-27 1993-09-21 Fujitsu Ltd 半導体装置
US5405454A (en) 1992-03-19 1995-04-11 Matsushita Electric Industrial Co., Ltd. Electrically insulated silicon structure and producing method therefor
JP2572003B2 (ja) * 1992-03-30 1997-01-16 三星電子株式会社 三次元マルチチャンネル構造を有する薄膜トランジスタの製造方法
JPH0793441B2 (ja) * 1992-04-24 1995-10-09 ヒュンダイ エレクトロニクス インダストリーズ カンパニー リミテッド 薄膜トランジスタ及びその製造方法
JPH065856A (ja) * 1992-06-19 1994-01-14 Kawasaki Steel Corp 半導体装置
JP3196858B2 (ja) * 1992-08-04 2001-08-06 シャープ株式会社 半導体装置の製造方法
JPH06177089A (ja) 1992-12-04 1994-06-24 Fujitsu Ltd 半導体装置の製造方法
KR960002088B1 (ko) 1993-02-17 1996-02-10 삼성전자주식회사 에스오아이(SOI : silicon on insulator) 구조의 반도체 장치 제조방법
US5357119A (en) 1993-02-19 1994-10-18 Board Of Regents Of The University Of California Field effect devices having short period superlattice structures using Si and Ge
JPH06310547A (ja) 1993-02-25 1994-11-04 Mitsubishi Electric Corp 半導体装置及びその製造方法
JPH0750421A (ja) 1993-05-06 1995-02-21 Siemens Ag Mos形電界効果トランジスタ
US5739544A (en) 1993-05-26 1998-04-14 Matsushita Electric Industrial Co., Ltd. Quantization functional device utilizing a resonance tunneling effect and method for producing the same
GB2282736B (en) 1993-05-28 1996-12-11 Nec Corp Radio base station for a mobile communications system
US6730549B1 (en) * 1993-06-25 2004-05-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for its preparation
JP3778581B2 (ja) 1993-07-05 2006-05-24 三菱電機株式会社 半導体装置およびその製造方法
JP3460863B2 (ja) * 1993-09-17 2003-10-27 三菱電機株式会社 半導体装置の製造方法
JPH07161984A (ja) * 1993-12-06 1995-06-23 Mitsubishi Electric Corp 半導体集積回路装置
US5479033A (en) 1994-05-27 1995-12-26 Sandia Corporation Complementary junction heterostructure field-effect transistor
JP3317582B2 (ja) * 1994-06-01 2002-08-26 菱電セミコンダクタシステムエンジニアリング株式会社 微細パターンの形成方法
JP3361922B2 (ja) 1994-09-13 2003-01-07 株式会社東芝 半導体装置
JP3378414B2 (ja) 1994-09-14 2003-02-17 株式会社東芝 半導体装置
JPH08153880A (ja) 1994-09-29 1996-06-11 Toshiba Corp 半導体装置及びその製造方法
US5602049A (en) 1994-10-04 1997-02-11 United Microelectronics Corporation Method of fabricating a buried structure SRAM cell
JPH08125152A (ja) * 1994-10-28 1996-05-17 Canon Inc 半導体装置、それを用いた相関演算装置、ad変換器、da変換器、信号処理システム
US5728594A (en) * 1994-11-02 1998-03-17 Texas Instruments Incorporated Method of making a multiple transistor integrated circuit with thick copper interconnect
US5576227A (en) 1994-11-02 1996-11-19 United Microelectronics Corp. Process for fabricating a recessed gate MOS device
JP3078720B2 (ja) 1994-11-02 2000-08-21 三菱電機株式会社 半導体装置およびその製造方法
GB2295488B (en) * 1994-11-24 1996-11-20 Toshiba Cambridge Res Center Semiconductor device
US5716879A (en) * 1994-12-15 1998-02-10 Goldstar Electron Company, Ltd. Method of making a thin film transistor
JPH08204191A (ja) 1995-01-20 1996-08-09 Sony Corp 電界効果トランジスタ及びその製造方法
US5665203A (en) 1995-04-28 1997-09-09 International Business Machines Corporation Silicon etching method
JP3303601B2 (ja) 1995-05-19 2002-07-22 日産自動車株式会社 溝型半導体装置
KR0165398B1 (ko) 1995-05-26 1998-12-15 윤종용 버티칼 트랜지스터의 제조방법
JPH0974205A (ja) * 1995-09-04 1997-03-18 Semiconductor Energy Lab Co Ltd 薄膜トランジスタ及びその作製方法
US5658806A (en) * 1995-10-26 1997-08-19 National Science Council Method for fabricating thin-film transistor with bottom-gate or dual-gate configuration
US5814895A (en) 1995-12-22 1998-09-29 Sony Corporation Static random access memory having transistor elements formed on side walls of a trench in a semiconductor substrate
KR100205442B1 (ko) 1995-12-26 1999-07-01 구본준 박막트랜지스터 및 그의 제조방법
US5595919A (en) 1996-02-20 1997-01-21 Chartered Semiconductor Manufacturing Pte Ltd. Method of making self-aligned halo process for reducing junction capacitance
DE19607209A1 (de) * 1996-02-26 1997-08-28 Gregor Kohlruss Reinigungsvorrichtung zum Reinigen von flächigen Gegenständen
JPH09293793A (ja) 1996-04-26 1997-11-11 Mitsubishi Electric Corp 薄膜トランジスタを有する半導体装置およびその製造方法
US5793088A (en) * 1996-06-18 1998-08-11 Integrated Device Technology, Inc. Structure for controlling threshold voltage of MOSFET
JP3710880B2 (ja) 1996-06-28 2005-10-26 株式会社東芝 不揮発性半導体記憶装置
TW556263B (en) 1996-07-11 2003-10-01 Semiconductor Energy Lab Semiconductor device and method of manufacturing the same
US5817560A (en) * 1996-09-12 1998-10-06 Advanced Micro Devices, Inc. Ultra short trench transistors and process for making same
US6399970B2 (en) 1996-09-17 2002-06-04 Matsushita Electric Industrial Co., Ltd. FET having a Si/SiGeC heterojunction channel
US6063675A (en) 1996-10-28 2000-05-16 Texas Instruments Incorporated Method of forming a MOSFET using a disposable gate with a sidewall dielectric
US6063677A (en) 1996-10-28 2000-05-16 Texas Instruments Incorporated Method of forming a MOSFET using a disposable gate and raised source and drain
US6163053A (en) * 1996-11-06 2000-12-19 Ricoh Company, Ltd. Semiconductor device having opposite-polarity region under channel
US5827769A (en) * 1996-11-20 1998-10-27 Intel Corporation Method for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrode
JPH10150185A (ja) 1996-11-20 1998-06-02 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5773331A (en) 1996-12-17 1998-06-30 International Business Machines Corporation Method for making single and double gate field effect transistors with sidewall source-drain contacts
US5908313A (en) 1996-12-31 1999-06-01 Intel Corporation Method of forming a transistor
JP4086926B2 (ja) 1997-01-29 2008-05-14 富士通株式会社 半導体装置及びその製造方法
US6676231B1 (en) * 1997-04-17 2004-01-13 Sligh Furniture Co. Modular furniture system
JPH118390A (ja) 1997-06-18 1999-01-12 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6251763B1 (en) 1997-06-30 2001-06-26 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing same
US6054355A (en) 1997-06-30 2000-04-25 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device which includes forming a dummy gate
JPH1140811A (ja) * 1997-07-22 1999-02-12 Hitachi Ltd 半導体装置およびその製造方法
US5952701A (en) 1997-08-18 1999-09-14 National Semiconductor Corporation Design and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor value
US5776821A (en) 1997-08-22 1998-07-07 Vlsi Technology, Inc. Method for forming a reduced width gate electrode
US6066869A (en) 1997-10-06 2000-05-23 Micron Technology, Inc. Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor
US5976767A (en) 1997-10-09 1999-11-02 Micron Technology, Inc. Ammonium hydroxide etch of photoresist masked silicon
US5856225A (en) 1997-11-24 1999-01-05 Chartered Semiconductor Manufacturing Ltd Creation of a self-aligned, ion implanted channel region, after source and drain formation
US6120846A (en) 1997-12-23 2000-09-19 Advanced Technology Materials, Inc. Method for the selective deposition of bismuth based ferroelectric thin films by chemical vapor deposition
US5888309A (en) * 1997-12-29 1999-03-30 Taiwan Semiconductor Manufacturing Company, Ltd. Lateral etch inhibited multiple for forming a via through a microelectronics layer susceptible to etching within a fluorine containing plasma followed by an oxygen containing plasma
US6117741A (en) 1998-01-09 2000-09-12 Texas Instruments Incorporated Method of forming a transistor having an improved sidewall gate structure
US6294416B1 (en) 1998-01-23 2001-09-25 Texas Instruments-Acer Incorporated Method of fabricating CMOS transistors with self-aligned planarization twin-well by using fewer mask counts
US6307235B1 (en) * 1998-03-30 2001-10-23 Micron Technology, Inc. Another technique for gated lateral bipolar transistors
US6097065A (en) * 1998-03-30 2000-08-01 Micron Technology, Inc. Circuits and methods for dual-gated transistors
US6087208A (en) 1998-03-31 2000-07-11 Advanced Micro Devices, Inc. Method for increasing gate capacitance by using both high and low dielectric gate material
US6215190B1 (en) 1998-05-12 2001-04-10 International Business Machines Corporation Borderless contact to diffusion with respect to gate conductor and methods for fabricating
US6232641B1 (en) 1998-05-29 2001-05-15 Kabushiki Kaisha Toshiba Semiconductor apparatus having elevated source and drain structure and manufacturing method therefor
US6114201A (en) 1998-06-01 2000-09-05 Texas Instruments-Acer Incorporated Method of manufacturing a multiple fin-shaped capacitor for high density DRAMs
US6317444B1 (en) 1998-06-12 2001-11-13 Agere System Optoelectronics Guardian Corp. Optical device including carbon-doped contact layers
US6165880A (en) 1998-06-15 2000-12-26 Taiwan Semiconductor Manufacturing Company Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits
US6130123A (en) 1998-06-30 2000-10-10 Intel Corporation Method for making a complementary metal gate electrode technology
JP2000037842A (ja) 1998-07-27 2000-02-08 Dainippon Printing Co Ltd 電磁波吸収化粧材
US6696366B1 (en) 1998-08-17 2004-02-24 Lam Research Corporation Technique for etching a low capacitance dielectric layer
JP2000156502A (ja) 1998-09-21 2000-06-06 Texas Instr Inc <Ti> 集積回路及び方法
US5985726A (en) 1998-11-06 1999-11-16 Advanced Micro Devices, Inc. Damascene process for forming ultra-shallow source/drain extensions and pocket in ULSI MOSFET
US6114206A (en) 1998-11-06 2000-09-05 Advanced Micro Devices, Inc. Multiple threshold voltage transistor implemented by a damascene process
US6262456B1 (en) 1998-11-06 2001-07-17 Advanced Micro Devices, Inc. Integrated circuit having transistors with different threshold voltages
US6153485A (en) 1998-11-09 2000-11-28 Chartered Semiconductor Manufacturing Ltd. Salicide formation on narrow poly lines by pulling back of spacer
US6200865B1 (en) 1998-12-04 2001-03-13 Advanced Micro Devices, Inc. Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gate
US6362111B1 (en) 1998-12-09 2002-03-26 Texas Instruments Incorporated Tunable gate linewidth reduction process
TW449919B (en) 1998-12-18 2001-08-11 Koninkl Philips Electronics Nv A method of manufacturing a semiconductor device
TW406312B (en) 1998-12-18 2000-09-21 United Microelectronics Corp The method of etching doped poly-silicon
US6380558B1 (en) * 1998-12-29 2002-04-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
US6150222A (en) 1999-01-07 2000-11-21 Advanced Micro Devices, Inc. Method of making a high performance transistor with elevated spacer formation and self-aligned channel regions
FR2788629B1 (fr) 1999-01-15 2003-06-20 Commissariat Energie Atomique Transistor mis et procede de fabrication d'un tel transistor sur un substrat semiconducteur
US6174820B1 (en) 1999-02-16 2001-01-16 Sandia Corporation Use of silicon oxynitride as a sacrificial material for microelectromechanical devices
JP2000243854A (ja) 1999-02-22 2000-09-08 Toshiba Corp 半導体装置及びその製造方法
US6093621A (en) 1999-04-05 2000-07-25 Vanguard International Semiconductor Corp. Method of forming shallow trench isolation
US7045468B2 (en) 1999-04-09 2006-05-16 Intel Corporation Isolated junction structure and method of manufacture
US6459123B1 (en) 1999-04-30 2002-10-01 Infineon Technologies Richmond, Lp Double gated transistor
DE60001601T2 (de) 1999-06-18 2003-12-18 Lucent Technologies Inc Fertigungsverfahren zur Herstellung eines CMOS integrieten Schaltkreises mit vertikalen Transistoren
JP2001015704A (ja) 1999-06-29 2001-01-19 Hitachi Ltd 半導体集積回路
US6218309B1 (en) 1999-06-30 2001-04-17 Lam Research Corporation Method of achieving top rounding and uniform etch depths while etching shallow trench isolation features
US6501131B1 (en) 1999-07-22 2002-12-31 International Business Machines Corporation Transistors having independently adjustable parameters
TW432594B (en) 1999-07-31 2001-05-01 Taiwan Semiconductor Mfg Manufacturing method for shallow trench isolation
US6259135B1 (en) 1999-09-24 2001-07-10 International Business Machines Corporation MOS transistors structure for reducing the size of pitch limited circuits
FR2799305B1 (fr) 1999-10-05 2004-06-18 St Microelectronics Sa Procede de fabrication d'un dispositif semi-conducteur a grille enveloppante et dispositif obtenu
US6355532B1 (en) * 1999-10-06 2002-03-12 Lsi Logic Corporation Subtractive oxidation method of fabricating a short-length and vertically-oriented channel, dual-gate, CMOS FET
EP1091413A3 (en) * 1999-10-06 2005-01-12 Lsi Logic Corporation Fully-depleted, fully-inverted, short-length and vertical channel, dual-gate, cmos fet
US6541829B2 (en) 1999-12-03 2003-04-01 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US6252284B1 (en) * 1999-12-09 2001-06-26 International Business Machines Corporation Planarized silicon fin device
KR100311049B1 (ko) 1999-12-13 2001-10-12 윤종용 불휘발성 반도체 메모리장치 및 그의 제조방법
US6303479B1 (en) 1999-12-16 2001-10-16 Spinnaker Semiconductor, Inc. Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts
JP4923318B2 (ja) * 1999-12-17 2012-04-25 ソニー株式会社 不揮発性半導体記憶装置およびその動作方法
JP4194237B2 (ja) 1999-12-28 2008-12-10 株式会社リコー 電界効果トランジスタを用いた電圧発生回路及び基準電圧源回路
US7391087B2 (en) 1999-12-30 2008-06-24 Intel Corporation MOS transistor structure and method of fabrication
JP3613113B2 (ja) 2000-01-21 2005-01-26 日本電気株式会社 半導体装置およびその製造方法
US6319807B1 (en) 2000-02-07 2001-11-20 United Microelectronics Corp. Method for forming a semiconductor device by using reverse-offset spacer process
JP3846706B2 (ja) * 2000-02-23 2006-11-15 信越半導体株式会社 ウエーハ外周面取部の研磨方法及び研磨装置
US6483156B1 (en) * 2000-03-16 2002-11-19 International Business Machines Corporation Double planar gated SOI MOSFET structure
FR2806832B1 (fr) 2000-03-22 2002-10-25 Commissariat Energie Atomique Transistor mos a source et drain metalliques, et procede de fabrication d'un tel transistor
JP3906005B2 (ja) 2000-03-27 2007-04-18 株式会社東芝 半導体装置の製造方法
KR100332834B1 (ko) 2000-03-29 2002-04-15 윤덕용 비등방성 식각을 이용한 서브마이크론 게이트 제조 방법
TW466606B (en) 2000-04-20 2001-12-01 United Microelectronics Corp Manufacturing method for dual metal gate electrode
JP2001338987A (ja) 2000-05-26 2001-12-07 Nec Microsystems Ltd Mosトランジスタのシャロートレンチ分離領域の形成方法
FR2810161B1 (fr) 2000-06-09 2005-03-11 Commissariat Energie Atomique Memoire electronique a architecture damascene et procede de realisation d'une telle memoire
US6526996B1 (en) 2000-06-12 2003-03-04 Promos Technologies, Inc. Dry clean method instead of traditional wet clean after metal etch
US6391782B1 (en) 2000-06-20 2002-05-21 Advanced Micro Devices, Inc. Process for forming multiple active lines and gate-all-around MOSFET
KR100545706B1 (ko) 2000-06-28 2006-01-24 주식회사 하이닉스반도체 반도체 소자 제조방법
EP1299914B1 (de) 2000-07-04 2008-04-02 Qimonda AG Feldeffekttransistor
JP2002047034A (ja) 2000-07-31 2002-02-12 Shinetsu Quartz Prod Co Ltd プラズマを利用したプロセス装置用の石英ガラス治具
US20020011612A1 (en) * 2000-07-31 2002-01-31 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US6403981B1 (en) 2000-08-07 2002-06-11 Advanced Micro Devices, Inc. Double gate transistor having a silicon/germanium channel region
KR100338778B1 (ko) * 2000-08-21 2002-05-31 윤종용 선택적 실리사이드 공정을 이용한 모스 트랜지스터의제조방법
US6358800B1 (en) 2000-09-18 2002-03-19 Vanguard International Semiconductor Corporation Method of forming a MOSFET with a recessed-gate having a channel length beyond photolithography limit
US6387820B1 (en) 2000-09-19 2002-05-14 Advanced Micro Devices, Inc. BC13/AR chemistry for metal overetching on a high density plasma etcher
JP2002100762A (ja) 2000-09-22 2002-04-05 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP4044276B2 (ja) * 2000-09-28 2008-02-06 株式会社東芝 半導体装置及びその製造方法
US6562665B1 (en) * 2000-10-16 2003-05-13 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology
US7163864B1 (en) 2000-10-18 2007-01-16 International Business Machines Corporation Method of fabricating semiconductor side wall fin
US6645840B2 (en) 2000-10-19 2003-11-11 Texas Instruments Incorporated Multi-layered polysilicon process
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6716684B1 (en) * 2000-11-13 2004-04-06 Advanced Micro Devices, Inc. Method of making a self-aligned triple gate silicon-on-insulator device
US6396108B1 (en) * 2000-11-13 2002-05-28 Advanced Micro Devices, Inc. Self-aligned double gate silicon-on-insulator (SOI) device
US6472258B1 (en) 2000-11-13 2002-10-29 International Business Machines Corporation Double gate trench transistor
US6479866B1 (en) 2000-11-14 2002-11-12 Advanced Micro Devices, Inc. SOI device with self-aligned selective damage implant, and method
JP2002198441A (ja) 2000-11-16 2002-07-12 Hynix Semiconductor Inc 半導体素子のデュアル金属ゲート形成方法
CN101465295A (zh) 2000-11-22 2009-06-24 株式会社日立制作所 半导体器件及其制造方法
US6552401B1 (en) 2000-11-27 2003-04-22 Micron Technology Use of gate electrode workfunction to improve DRAM refresh
US20020100942A1 (en) 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6921947B2 (en) 2000-12-15 2005-07-26 Renesas Technology Corp. Semiconductor device having recessed isolation insulation film
US6413877B1 (en) * 2000-12-22 2002-07-02 Lam Research Corporation Method of preventing damage to organo-silicate-glass materials during resist stripping
JP2002198368A (ja) * 2000-12-26 2002-07-12 Nec Corp 半導体装置の製造方法
US6537901B2 (en) 2000-12-29 2003-03-25 Hynix Semiconductor Inc. Method of manufacturing a transistor in a semiconductor device
TW561530B (en) 2001-01-03 2003-11-11 Macronix Int Co Ltd Process for fabricating CMOS transistor of IC devices employing double spacers for preventing short-channel effect
US6975014B1 (en) 2001-01-09 2005-12-13 Advanced Micro Devices, Inc. Method for making an ultra thin FDSOI device with improved short-channel performance
US6359311B1 (en) 2001-01-17 2002-03-19 Taiwan Semiconductor Manufacturing Co., Ltd. Quasi-surrounding gate and a method of fabricating a silicon-on-insulator semiconductor device with the same
US6403434B1 (en) 2001-02-09 2002-06-11 Advanced Micro Devices, Inc. Process for manufacturing MOS transistors having elevated source and drain regions and a high-k gate dielectric
US6475890B1 (en) * 2001-02-12 2002-11-05 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology
JP2002246310A (ja) 2001-02-14 2002-08-30 Sony Corp 半導体薄膜の形成方法及び半導体装置の製造方法、これらの方法の実施に使用する装置、並びに電気光学装置
US6475869B1 (en) * 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
US6630388B2 (en) * 2001-03-13 2003-10-07 National Institute Of Advanced Industrial Science And Technology Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same
TW582071B (en) 2001-03-20 2004-04-01 Macronix Int Co Ltd Method for etching metal in a semiconductor
JP3940565B2 (ja) 2001-03-29 2007-07-04 株式会社東芝 半導体装置及びその製造方法
JP2002298051A (ja) 2001-03-30 2002-10-11 Mizuho Bank Ltd ポイント交換サービス・システム
US6458662B1 (en) 2001-04-04 2002-10-01 Advanced Micro Devices, Inc. Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed
KR100414217B1 (ko) 2001-04-12 2004-01-07 삼성전자주식회사 게이트 올 어라운드형 트랜지스터를 가진 반도체 장치 및그 형성 방법
US6645861B2 (en) 2001-04-18 2003-11-11 International Business Machines Corporation Self-aligned silicide process for silicon sidewall source and drain contacts
US6787402B1 (en) 2001-04-27 2004-09-07 Advanced Micro Devices, Inc. Double-gate vertical MOSFET transistor and fabrication method
US6902947B2 (en) 2001-05-07 2005-06-07 Applied Materials, Inc. Integrated method for release and passivation of MEMS structures
SG112804A1 (en) * 2001-05-10 2005-07-28 Inst Of Microelectronics Sloped trench etching process
KR100363332B1 (en) 2001-05-23 2002-12-05 Samsung Electronics Co Ltd Method for forming semiconductor device having gate all-around type transistor
US6635923B2 (en) 2001-05-24 2003-10-21 International Business Machines Corporation Damascene double-gate MOSFET with vertical channel regions
US6506692B2 (en) 2001-05-30 2003-01-14 Intel Corporation Method of making a semiconductor device using a silicon carbide hard mask
AU785016B2 (en) * 2001-06-14 2006-08-24 Rohm And Haas Company Semi-continuous bimodal emulsion polymerization
US6737333B2 (en) 2001-07-03 2004-05-18 Texas Instruments Incorporated Semiconductor device isolation structure and method of forming
JP2003017508A (ja) * 2001-07-05 2003-01-17 Nec Corp 電界効果トランジスタ
US6501141B1 (en) 2001-08-13 2002-12-31 Taiwan Semiconductor Manufacturing Company, Ltd Self-aligned contact with improved isolation and method for forming
US6534807B2 (en) 2001-08-13 2003-03-18 International Business Machines Corporation Local interconnect junction on insulator (JOI) structure
US6764965B2 (en) 2001-08-17 2004-07-20 United Microelectronics Corp. Method for improving the coating capability of low-k dielectric layer
JP2003100902A (ja) 2001-09-21 2003-04-04 Mitsubishi Electric Corp 半導体装置の製造方法
US6689650B2 (en) * 2001-09-27 2004-02-10 International Business Machines Corporation Fin field effect transistor with self-aligned gate
US6492212B1 (en) 2001-10-05 2002-12-10 International Business Machines Corporation Variable threshold voltage double gated transistors and method of fabrication
US20030085194A1 (en) * 2001-11-07 2003-05-08 Hopkins Dean A. Method for fabricating close spaced mirror arrays
US7385262B2 (en) * 2001-11-27 2008-06-10 The Board Of Trustees Of The Leland Stanford Junior University Band-structure modulation of nano-structures in an electric field
US6657259B2 (en) * 2001-12-04 2003-12-02 International Business Machines Corporation Multiple-plane FinFET CMOS
US6967351B2 (en) 2001-12-04 2005-11-22 International Business Machines Corporation Finfet SRAM cell using low mobility plane for cell stability and method for forming
US6610576B2 (en) * 2001-12-13 2003-08-26 International Business Machines Corporation Method for forming asymmetric dual gate transistor
US6555879B1 (en) 2002-01-11 2003-04-29 Advanced Micro Devices, Inc. SOI device with metal source/drain and method of fabrication
US6722946B2 (en) 2002-01-17 2004-04-20 Nutool, Inc. Advanced chemical mechanical polishing system with smart endpoint detection
US6583469B1 (en) 2002-01-28 2003-06-24 International Business Machines Corporation Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same
KR100442089B1 (ko) * 2002-01-29 2004-07-27 삼성전자주식회사 노치된 게이트 전극을 갖는 모스 트랜지스터의 제조방법
KR100458288B1 (ko) 2002-01-30 2004-11-26 한국과학기술원 이중-게이트 FinFET 소자 및 그 제조방법
DE10203998A1 (de) 2002-02-01 2003-08-21 Infineon Technologies Ag Verfahren zum Herstellen einer zackenförmigen Struktur, Verfahren zum Herstellen eines Transistors, Verfahren zum Herstellen eines Floating Gate-Transistors, Transistor, Floating Gate-Transistor und Speicher-Anordnung
JP2003229575A (ja) * 2002-02-04 2003-08-15 Hitachi Ltd 集積半導体装置及びその製造方法
US6784071B2 (en) 2003-01-31 2004-08-31 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement
US20030151077A1 (en) * 2002-02-13 2003-08-14 Leo Mathew Method of forming a vertical double gate semiconductor device and structure thereof
JP3782021B2 (ja) * 2002-02-22 2006-06-07 株式会社東芝 半導体装置、半導体装置の製造方法、半導体基板の製造方法
US6660598B2 (en) 2002-02-26 2003-12-09 International Business Machines Corporation Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region
JP4370104B2 (ja) 2002-03-05 2009-11-25 シャープ株式会社 半導体記憶装置
US6639827B2 (en) 2002-03-12 2003-10-28 Intel Corporation Low standby power using shadow storage
US6635909B2 (en) * 2002-03-19 2003-10-21 International Business Machines Corporation Strained fin FETs structure and method
US6605498B1 (en) 2002-03-29 2003-08-12 Intel Corporation Semiconductor transistor having a backfilled channel material
FR2838238B1 (fr) 2002-04-08 2005-04-15 St Microelectronics Sa Dispositif semiconducteur a grille enveloppante encapsule dans un milieu isolant
US6784076B2 (en) 2002-04-08 2004-08-31 Micron Technology, Inc. Process for making a silicon-on-insulator ledge by implanting ions from silicon source
US6762469B2 (en) 2002-04-19 2004-07-13 International Business Machines Corporation High performance CMOS device structure with mid-gap metal gate
US6713396B2 (en) * 2002-04-29 2004-03-30 Hewlett-Packard Development Company, L.P. Method of fabricating high density sub-lithographic features on a substrate
US6537885B1 (en) 2002-05-09 2003-03-25 Infineon Technologies Ag Transistor and method of manufacturing a transistor having a shallow junction formation using a two step EPI layer
US6642090B1 (en) 2002-06-03 2003-11-04 International Business Machines Corporation Fin FET devices from bulk semiconductor and method for forming
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US6680240B1 (en) * 2002-06-25 2004-01-20 Advanced Micro Devices, Inc. Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide
US7105891B2 (en) 2002-07-15 2006-09-12 Texas Instruments Incorporated Gate structure and method
US6974729B2 (en) 2002-07-16 2005-12-13 Interuniversitair Microelektronica Centrum (Imec) Integrated semiconductor fin device and a method for manufacturing such device
US6705571B2 (en) 2002-07-22 2004-03-16 Northrop Grumman Corporation System and method for loading stores on an aircraft
KR100477543B1 (ko) 2002-07-26 2005-03-18 동부아남반도체 주식회사 단채널 트랜지스터 형성방법
US6919238B2 (en) 2002-07-29 2005-07-19 Intel Corporation Silicon on insulator (SOI) transistor and methods of fabrication
US6921702B2 (en) 2002-07-30 2005-07-26 Micron Technology Inc. Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
EP1387395B1 (en) * 2002-07-31 2016-11-23 Micron Technology, Inc. Method for manufacturing semiconductor integrated circuit structures
JP2004071996A (ja) 2002-08-09 2004-03-04 Hitachi Ltd 半導体集積回路装置の製造方法
US6984585B2 (en) 2002-08-12 2006-01-10 Applied Materials Inc Method for removal of residue from a magneto-resistive random access memory (MRAM) film stack using a sacrificial mask layer
US6891234B1 (en) 2004-01-07 2005-05-10 Acorn Technologies, Inc. Transistor with workfunction-induced charge layer
US6833556B2 (en) 2002-08-12 2004-12-21 Acorn Technologies, Inc. Insulated gate field effect transistor having passivated schottky barriers to the channel
JP3865233B2 (ja) 2002-08-19 2007-01-10 富士通株式会社 Cmos集積回路装置
US7358121B2 (en) 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US7163851B2 (en) 2002-08-26 2007-01-16 International Business Machines Corporation Concurrent Fin-FET and thick-body device fabrication
JP5179692B2 (ja) 2002-08-30 2013-04-10 富士通セミコンダクター株式会社 半導体記憶装置及びその製造方法
US6770516B2 (en) 2002-09-05 2004-08-03 Taiwan Semiconductor Manufacturing Company Method of forming an N channel and P channel FINFET device on the same semiconductor substrate
JP3651802B2 (ja) 2002-09-12 2005-05-25 株式会社東芝 半導体装置の製造方法
US6794313B1 (en) * 2002-09-20 2004-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Oxidation process to improve polysilicon sidewall roughness
JP3556651B2 (ja) 2002-09-27 2004-08-18 沖電気工業株式会社 半導体装置の製造方法
US6800910B2 (en) 2002-09-30 2004-10-05 Advanced Micro Devices, Inc. FinFET device incorporating strained silicon in the channel region
KR100481209B1 (ko) 2002-10-01 2005-04-08 삼성전자주식회사 다중 채널을 갖는 모스 트랜지스터 및 그 제조방법
JP4294935B2 (ja) 2002-10-17 2009-07-15 株式会社ルネサステクノロジ 半導体装置
US6706571B1 (en) * 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
US6833588B2 (en) 2002-10-22 2004-12-21 Advanced Micro Devices, Inc. Semiconductor device having a U-shaped gate structure
US6706581B1 (en) 2002-10-29 2004-03-16 Taiwan Semiconductor Manufacturing Company Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices
US6787439B2 (en) * 2002-11-08 2004-09-07 Advanced Micro Devices, Inc. Method using planarizing gate material to improve gate critical dimension in semiconductor devices
US6611029B1 (en) * 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates
US6709982B1 (en) * 2002-11-26 2004-03-23 Advanced Micro Devices, Inc. Double spacer FinFET formation
US6855990B2 (en) 2002-11-26 2005-02-15 Taiwan Semiconductor Manufacturing Co., Ltd Strained-channel multiple-gate transistor
US6825506B2 (en) 2002-11-27 2004-11-30 Intel Corporation Field effect transistor and method of fabrication
US6821834B2 (en) 2002-12-04 2004-11-23 Yoshiyuki Ando Ion implantation methods and transistor cell layout for fin type transistors
US6645797B1 (en) * 2002-12-06 2003-11-11 Advanced Micro Devices, Inc. Method for forming fins in a FinFET device using sacrificial carbon layer
KR100487922B1 (ko) 2002-12-06 2005-05-06 주식회사 하이닉스반도체 반도체소자의 트랜지스터 및 그 형성방법
US6686231B1 (en) 2002-12-06 2004-02-03 Advanced Micro Devices, Inc. Damascene gate process with sacrificial oxide in semiconductor devices
US7728360B2 (en) * 2002-12-06 2010-06-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple-gate transistor structure
US7214991B2 (en) * 2002-12-06 2007-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. CMOS inverters configured using multiple-gate transistors
US6867425B2 (en) * 2002-12-13 2005-03-15 Intel Corporation Lateral phase change memory and method therefor
US6869868B2 (en) 2002-12-13 2005-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a MOSFET device with metal containing gate structures
US6794718B2 (en) 2002-12-19 2004-09-21 International Business Machines Corporation High mobility crystalline planes in double-gate CMOS technology
DE60236375D1 (de) 2002-12-20 2010-06-24 Ibm Integrierte anitfuse-struktur für finfet- und cmos-vorrichtungen
US6780694B2 (en) 2003-01-08 2004-08-24 International Business Machines Corporation MOS transistor
JP2004221334A (ja) * 2003-01-15 2004-08-05 Seiko Epson Corp 金属素子形成方法、半導体装置の製造方法及び電子デバイスの製造方法、半導体装置及び電子デバイス、並びに電子機器
US7259425B2 (en) 2003-01-23 2007-08-21 Advanced Micro Devices, Inc. Tri-gate and gate around MOSFET devices and methods for making same
US6803631B2 (en) 2003-01-23 2004-10-12 Advanced Micro Devices, Inc. Strained channel finfet
US6762483B1 (en) 2003-01-23 2004-07-13 Advanced Micro Devices, Inc. Narrow fin FinFET
US6885055B2 (en) 2003-02-04 2005-04-26 Lee Jong-Ho Double-gate FinFET device and fabricating method thereof
KR100543472B1 (ko) 2004-02-11 2006-01-20 삼성전자주식회사 소오스/드레인 영역에 디플리션 방지막을 구비하는 반도체소자 및 그 형성 방법
US7304336B2 (en) * 2003-02-13 2007-12-04 Massachusetts Institute Of Technology FinFET structure and method to make the same
US6855606B2 (en) * 2003-02-20 2005-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-rod devices
US7105894B2 (en) * 2003-02-27 2006-09-12 Taiwan Semiconductor Manufacturing Co., Ltd. Contacts to semiconductor fin devices
KR100499159B1 (ko) 2003-02-28 2005-07-01 삼성전자주식회사 리세스 채널을 갖는 반도체장치 및 그 제조방법
US6800885B1 (en) 2003-03-12 2004-10-05 Advance Micro Devices, Inc. Asymmetrical double gate or all-around gate MOSFET devices and methods for making same
US6787854B1 (en) 2003-03-12 2004-09-07 Advanced Micro Devices, Inc. Method for forming a fin in a finFET device
US6716690B1 (en) * 2003-03-12 2004-04-06 Advanced Micro Devices, Inc. Uniformly doped source/drain junction in a double-gate MOSFET
TW582099B (en) 2003-03-13 2004-04-01 Ind Tech Res Inst Method of adhering material layer on transparent substrate and method of forming single crystal silicon on transparent substrate
JP4563652B2 (ja) * 2003-03-13 2010-10-13 シャープ株式会社 メモリ機能体および微粒子形成方法並びにメモリ素子、半導体装置および電子機器
US6844238B2 (en) * 2003-03-26 2005-01-18 Taiwan Semiconductor Manufacturing Co., Ltd Multiple-gate transistors with improved gate control
US20040191980A1 (en) * 2003-03-27 2004-09-30 Rafael Rios Multi-corner FET for better immunity from short channel effects
US6790733B1 (en) * 2003-03-28 2004-09-14 International Business Machines Corporation Preserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer
US6764884B1 (en) * 2003-04-03 2004-07-20 Advanced Micro Devices, Inc. Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device
TWI231994B (en) * 2003-04-04 2005-05-01 Univ Nat Taiwan Strained Si FinFET
US6902962B2 (en) 2003-04-04 2005-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Silicon-on-insulator chip with multiple crystal orientations
US7442415B2 (en) 2003-04-11 2008-10-28 Sharp Laboratories Of America, Inc. Modulated temperature method of atomic layer deposition (ALD) of high dielectric constant films
JP2004319704A (ja) 2003-04-15 2004-11-11 Seiko Instruments Inc 半導体装置
TW200506093A (en) 2003-04-21 2005-02-16 Aviza Tech Inc System and method for forming multi-component films
JPWO2004097943A1 (ja) 2003-04-28 2006-07-13 松下電器産業株式会社 半導体装置とその製造方法
US6867433B2 (en) 2003-04-30 2005-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
JP3976703B2 (ja) * 2003-04-30 2007-09-19 エルピーダメモリ株式会社 半導体装置の製造方法
US6838322B2 (en) 2003-05-01 2005-01-04 Freescale Semiconductor, Inc. Method for forming a double-gated semiconductor device
US6909147B2 (en) 2003-05-05 2005-06-21 International Business Machines Corporation Multi-height FinFETS
US6765303B1 (en) 2003-05-06 2004-07-20 Advanced Micro Devices, Inc. FinFET-based SRAM cell
EP1643560A4 (en) * 2003-05-30 2007-04-11 Matsushita Electric Ind Co Ltd SEMICONDUCTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF
US6830998B1 (en) 2003-06-17 2004-12-14 Advanced Micro Devices, Inc. Gate dielectric quality for replacement metal gate transistors
US7045401B2 (en) * 2003-06-23 2006-05-16 Sharp Laboratories Of America, Inc. Strained silicon finFET device
US6911383B2 (en) 2003-06-26 2005-06-28 International Business Machines Corporation Hybrid planar and finFET CMOS devices
US20040262683A1 (en) * 2003-06-27 2004-12-30 Bohr Mark T. PMOS transistor strain optimization with raised junction regions
US7456476B2 (en) * 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US6909151B2 (en) * 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US6960517B2 (en) * 2003-06-30 2005-11-01 Intel Corporation N-gate transistor
US6716686B1 (en) * 2003-07-08 2004-04-06 Advanced Micro Devices, Inc. Method for forming channels in a finfet device
US6921982B2 (en) * 2003-07-21 2005-07-26 International Business Machines Corporation FET channel having a strained lattice structure along multiple surfaces
US7013447B2 (en) * 2003-07-22 2006-03-14 Freescale Semiconductor, Inc. Method for converting a planar transistor design to a vertical double gate transistor design
KR100487566B1 (ko) 2003-07-23 2005-05-03 삼성전자주식회사 핀 전계 효과 트랜지스터 및 그 형성 방법
KR100487567B1 (ko) 2003-07-24 2005-05-03 삼성전자주식회사 핀 전계효과 트랜지스터 형성 방법
EP1519420A2 (en) 2003-09-25 2005-03-30 Interuniversitaire Microelectronica Centrum vzw ( IMEC) Multiple gate semiconductor device and method for forming same
US6835618B1 (en) * 2003-08-05 2004-12-28 Advanced Micro Devices, Inc. Epitaxially grown fin for FinFET
US7172943B2 (en) * 2003-08-13 2007-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-gate transistors formed on bulk substrates
KR100496891B1 (ko) 2003-08-14 2005-06-23 삼성전자주식회사 핀 전계효과 트랜지스터를 위한 실리콘 핀 및 그 제조 방법
US7355253B2 (en) 2003-08-22 2008-04-08 International Business Machines Corporation Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates
WO2005022637A1 (ja) * 2003-08-28 2005-03-10 Nec Corporation フィン型電界効果トランジスタを有する半導体装置
US6998301B1 (en) 2003-09-03 2006-02-14 Advanced Micro Devices, Inc. Method for forming a tri-gate MOSFET
US6877728B2 (en) 2003-09-04 2005-04-12 Lakin Manufacturing Corporation Suspension assembly having multiple torsion members which cooperatively provide suspension to a wheel
JP4439358B2 (ja) 2003-09-05 2010-03-24 株式会社東芝 電界効果トランジスタ及びその製造方法
US7170126B2 (en) 2003-09-16 2007-01-30 International Business Machines Corporation Structure of vertical strained silicon devices
US6970373B2 (en) 2003-10-02 2005-11-29 Intel Corporation Method and apparatus for improving stability of a 6T CMOS SRAM cell
US7612416B2 (en) * 2003-10-09 2009-11-03 Nec Corporation Semiconductor device having a conductive portion below an interlayer insulating film and method for producing the same
US20050139860A1 (en) 2003-10-22 2005-06-30 Snyder John P. Dynamic schottky barrier MOSFET device and method of manufacture
US6946377B2 (en) 2003-10-29 2005-09-20 Texas Instruments Incorporated Multiple-gate MOSFET device with lithography independent silicon body thickness and methods for fabricating the same
KR100515061B1 (ko) 2003-10-31 2005-09-14 삼성전자주식회사 핀 전계 효과 트랜지스터를 갖는 반도체 소자 및 그 형성방법
US7138320B2 (en) 2003-10-31 2006-11-21 Advanced Micro Devices, Inc. Advanced technique for forming a transistor having raised drain and source regions
US6867460B1 (en) 2003-11-05 2005-03-15 International Business Machines Corporation FinFET SRAM cell with chevron FinFET logic
US6885072B1 (en) 2003-11-18 2005-04-26 Applied Intellectual Properties Co., Ltd. Nonvolatile memory with undercut trapping structure
US7545001B2 (en) 2003-11-25 2009-06-09 Taiwan Semiconductor Manufacturing Company Semiconductor device having high drive current and method of manufacture therefor
US7183137B2 (en) * 2003-12-01 2007-02-27 Taiwan Semiconductor Manufacturing Company Method for dicing semiconductor wafers
US7075150B2 (en) 2003-12-02 2006-07-11 International Business Machines Corporation Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique
US7018551B2 (en) 2003-12-09 2006-03-28 International Business Machines Corporation Pull-back method of forming fins in FinFets
US7388258B2 (en) * 2003-12-10 2008-06-17 International Business Machines Corporation Sectional field effect devices
JP2005183770A (ja) * 2003-12-22 2005-07-07 Mitsubishi Electric Corp 高周波用半導体装置
US7662689B2 (en) 2003-12-23 2010-02-16 Intel Corporation Strained transistor integration for CMOS
US7569882B2 (en) * 2003-12-23 2009-08-04 Interuniversitair Microelektronica Centrum (Imec) Non-volatile multibit memory cell and method of manufacturing thereof
US7223679B2 (en) 2003-12-24 2007-05-29 Intel Corporation Transistor gate electrode having conductor material layer
US7045407B2 (en) 2003-12-30 2006-05-16 Intel Corporation Amorphous etch stop for the anisotropic etching of substrates
US7105390B2 (en) 2003-12-30 2006-09-12 Intel Corporation Nonplanar transistors with metal gate electrodes
US7078282B2 (en) 2003-12-30 2006-07-18 Intel Corporation Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films
US7247578B2 (en) 2003-12-30 2007-07-24 Intel Corporation Method of varying etch selectivities of a film
US7705345B2 (en) * 2004-01-07 2010-04-27 International Business Machines Corporation High performance strained silicon FinFETs device and method for forming same
US6974736B2 (en) 2004-01-09 2005-12-13 International Business Machines Corporation Method of forming FET silicide gate structures incorporating inner spacers
US7056794B2 (en) 2004-01-09 2006-06-06 International Business Machines Corporation FET gate structure with metal gate electrode and silicide contact
US7268058B2 (en) 2004-01-16 2007-09-11 Intel Corporation Tri-gate transistors and methods to fabricate same
US7385247B2 (en) 2004-01-17 2008-06-10 Samsung Electronics Co., Ltd. At least penta-sided-channel type of FinFET transistor
JP2005209782A (ja) 2004-01-21 2005-08-04 Toshiba Corp 半導体装置
US7250645B1 (en) 2004-01-22 2007-07-31 Advanced Micro Devices, Inc. Reversed T-shaped FinFET
US7224029B2 (en) 2004-01-28 2007-05-29 International Business Machines Corporation Method and structure to create multiple device widths in FinFET technology in both bulk and SOI
KR100587672B1 (ko) 2004-02-02 2006-06-08 삼성전자주식회사 다마신 공법을 이용한 핀 트랜지스터 형성방법
JP2005236305A (ja) 2004-02-20 2005-09-02 Samsung Electronics Co Ltd トリプルゲートトランジスタを有する半導体素子及びその製造方法
US7060539B2 (en) * 2004-03-01 2006-06-13 International Business Machines Corporation Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby
JP4852694B2 (ja) 2004-03-02 2012-01-11 独立行政法人産業技術総合研究所 半導体集積回路およびその製造方法
US6921691B1 (en) 2004-03-18 2005-07-26 Infineon Technologies Ag Transistor with dopant-bearing metal in source and drain
US7701018B2 (en) * 2004-03-19 2010-04-20 Nec Corporation Semiconductor device and method for manufacturing same
KR100576361B1 (ko) 2004-03-23 2006-05-03 삼성전자주식회사 3차원 시모스 전계효과 트랜지스터 및 그것을 제조하는 방법
US7141480B2 (en) 2004-03-26 2006-11-28 Texas Instruments Incorporated Tri-gate low power device and method for manufacturing the same
US8450806B2 (en) 2004-03-31 2013-05-28 International Business Machines Corporation Method for fabricating strained silicon-on-insulator structures and strained silicon-on insulator structures formed thereby
US7154118B2 (en) * 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US20050224797A1 (en) * 2004-04-01 2005-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS fabricated on different crystallographic orientation substrates
US20050230763A1 (en) 2004-04-15 2005-10-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a microelectronic device with electrode perturbing sill
KR100642632B1 (ko) 2004-04-27 2006-11-10 삼성전자주식회사 반도체소자의 제조방법들 및 그에 의해 제조된 반도체소자들
US7084018B1 (en) 2004-05-05 2006-08-01 Advanced Micro Devices, Inc. Sacrificial oxide for minimizing box undercut in damascene FinFET
US20050255642A1 (en) 2004-05-11 2005-11-17 Chi-Wen Liu Method of fabricating inlaid structure
US6864540B1 (en) 2004-05-21 2005-03-08 International Business Machines Corp. High performance FET with elevated source/drain region
KR100625177B1 (ko) 2004-05-25 2006-09-20 삼성전자주식회사 멀티-브리지 채널형 모오스 트랜지스터의 제조 방법
US6955961B1 (en) * 2004-05-27 2005-10-18 Macronix International Co., Ltd. Method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution
KR100634372B1 (ko) 2004-06-04 2006-10-16 삼성전자주식회사 반도체 소자들 및 그 형성 방법들
US7452778B2 (en) * 2004-06-10 2008-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-wire devices and methods of fabrication
US7132360B2 (en) 2004-06-10 2006-11-07 Freescale Semiconductor, Inc. Method for treating a semiconductor surface to form a metal-containing layer
JP5056011B2 (ja) * 2004-06-10 2012-10-24 日本電気株式会社 半導体装置及びその製造方法、FinFETの製造方法
US7291886B2 (en) 2004-06-21 2007-11-06 International Business Machines Corporation Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs
KR100541657B1 (ko) * 2004-06-29 2006-01-11 삼성전자주식회사 멀티 게이트 트랜지스터의 제조방법 및 이에 의해 제조된멀티 게이트 트랜지스터
US8669145B2 (en) * 2004-06-30 2014-03-11 International Business Machines Corporation Method and structure for strained FinFET devices
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US20060040054A1 (en) 2004-08-18 2006-02-23 Pearlstein Ronald M Passivating ALD reactor chamber internal surfaces to prevent residue buildup
US20060043500A1 (en) * 2004-08-24 2006-03-02 Jian Chen Transistor structure with stress modification and capacitive reduction feature in a channel direction and method thereof
US7105934B2 (en) * 2004-08-30 2006-09-12 International Business Machines Corporation FinFET with low gate capacitance and low extrinsic resistance
US7250367B2 (en) 2004-09-01 2007-07-31 Micron Technology, Inc. Deposition methods using heteroleptic precursors
US7071064B2 (en) 2004-09-23 2006-07-04 Intel Corporation U-gate transistors and methods of fabrication
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US7332439B2 (en) 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7247547B2 (en) 2005-01-05 2007-07-24 International Business Machines Corporation Method of fabricating a field effect transistor having improved junctions
US7875547B2 (en) 2005-01-12 2011-01-25 Taiwan Semiconductor Manufacturing Co., Ltd. Contact hole structures and contact structures and fabrication methods thereof
US7470951B2 (en) * 2005-01-31 2008-12-30 Freescale Semiconductor, Inc. Hybrid-FET and its application as SRAM
US20060172480A1 (en) 2005-02-03 2006-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. Single metal gate CMOS device design
US20060180859A1 (en) * 2005-02-16 2006-08-17 Marko Radosavljevic Metal gate carbon nanotube transistor
DE102005008478B3 (de) * 2005-02-24 2006-10-26 Infineon Technologies Ag Verfahren zur Herstellung von sublithographischen Strukturen
US7238564B2 (en) 2005-03-10 2007-07-03 Taiwan Semiconductor Manufacturing Company Method of forming a shallow trench isolation structure
JP4825526B2 (ja) * 2005-03-28 2011-11-30 株式会社東芝 Fin型チャネルトランジスタおよびその製造方法
US7177177B2 (en) 2005-04-07 2007-02-13 International Business Machines Corporation Back-gate controlled read SRAM cell
KR100699839B1 (ko) 2005-04-21 2007-03-27 삼성전자주식회사 다중채널을 갖는 반도체 장치 및 그의 제조방법.
US7429536B2 (en) * 2005-05-23 2008-09-30 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7396781B2 (en) * 2005-06-09 2008-07-08 Micron Technology, Inc. Method and apparatus for adjusting feature size and position
US7319074B2 (en) 2005-06-13 2008-01-15 United Microelectronics Corp. Method of defining polysilicon patterns
JP4718908B2 (ja) * 2005-06-14 2011-07-06 株式会社東芝 半導体装置および半導体装置の製造方法
US7279375B2 (en) * 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US20070023795A1 (en) 2005-07-15 2007-02-01 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
US7348642B2 (en) * 2005-08-03 2008-03-25 International Business Machines Corporation Fin-type field effect transistor
US7352034B2 (en) 2005-08-25 2008-04-01 International Business Machines Corporation Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures
US7339241B2 (en) * 2005-08-31 2008-03-04 Freescale Semiconductor, Inc. FinFET structure with contacts
US7416943B2 (en) 2005-09-01 2008-08-26 Micron Technology, Inc. Peripheral gate stacks and recessed array gates
US7479421B2 (en) * 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US8513066B2 (en) 2005-10-25 2013-08-20 Freescale Semiconductor, Inc. Method of making an inverted-T channel transistor
KR100718159B1 (ko) * 2006-05-18 2007-05-14 삼성전자주식회사 와이어-타입 반도체 소자 및 그 제조 방법
US20080017890A1 (en) * 2006-06-30 2008-01-24 Sandisk 3D Llc Highly dense monolithic three dimensional memory array and method for forming
US7456471B2 (en) * 2006-09-15 2008-11-25 International Business Machines Corporation Field effect transistor with raised source/drain fin straps
US7646046B2 (en) * 2006-11-14 2010-01-12 Infineon Technologies Ag Field effect transistor with a fin structure
CA2669704A1 (en) * 2006-11-16 2008-05-22 Allergan, Inc. Sulfoximines as kinase inhibitors
US7678632B2 (en) * 2006-11-17 2010-03-16 Infineon Technologies Ag MuGFET with increased thermal mass
US20080128797A1 (en) * 2006-11-30 2008-06-05 International Business Machines Corporation Structure and method for multiple height finfet devices
US7655989B2 (en) * 2006-11-30 2010-02-02 International Business Machines Corporation Triple gate and double gate finFETs with different vertical dimension fins
US20080212392A1 (en) * 2007-03-02 2008-09-04 Infineon Technologies Multiple port mugfet sram
JP4406439B2 (ja) * 2007-03-29 2010-01-27 株式会社東芝 半導体装置の製造方法

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109065611A (zh) * 2011-12-23 2018-12-21 英特尔公司 具有非分立的源极区和漏极区的纳米线结构
US11552197B2 (en) 2011-12-23 2023-01-10 Google Llc Nanowire structures having non-discrete source and drain regions
CN103296083A (zh) * 2012-02-27 2013-09-11 中国科学院微电子研究所 半导体场效应晶体管及其制作方法
CN109148564A (zh) * 2017-06-16 2019-01-04 韩国科学技术研究院 场效应晶体管、生物传感器及其制造方法
CN109427593A (zh) * 2017-08-31 2019-03-05 台湾积体电路制造股份有限公司 制造半导体装置的方法
CN109427593B (zh) * 2017-08-31 2021-11-02 台湾积体电路制造股份有限公司 制造半导体装置的方法
CN110164969A (zh) * 2018-02-13 2019-08-23 隽佾科技有限公司 波浪式场效晶体管结构
CN110190122A (zh) * 2018-02-23 2019-08-30 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
CN110190122B (zh) * 2018-02-23 2022-07-12 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
TWI712120B (zh) * 2018-06-19 2020-12-01 日商松下半導體解決方案股份有限公司 半導體裝置
TWI733620B (zh) * 2018-06-19 2021-07-11 日商新唐科技日本股份有限公司 半導體裝置
TWI809539B (zh) * 2021-07-28 2023-07-21 南亞科技股份有限公司 具有不同寬度之導電接觸點的半導體元件結構及其製備方法

Also Published As

Publication number Publication date
DE112006001735B4 (de) 2010-11-18
TWI314779B (en) 2009-09-11
US7898041B2 (en) 2011-03-01
GB2442379B (en) 2011-03-09
GB2442379A (en) 2008-04-02
JP2008544558A (ja) 2008-12-04
US7279375B2 (en) 2007-10-09
CN101208805B (zh) 2014-07-30
WO2007005697A2 (en) 2007-01-11
KR20080024168A (ko) 2008-03-17
TW200715528A (en) 2007-04-16
GB0724762D0 (en) 2008-01-30
DE112006001735T5 (de) 2008-08-28
US20070001219A1 (en) 2007-01-04
WO2007005697A3 (en) 2007-04-12
KR101021369B1 (ko) 2011-03-14
US20080258207A1 (en) 2008-10-23

Similar Documents

Publication Publication Date Title
CN101208805B (zh) 纳米尺度沟道晶体管的块接触结构
CN110800113B (zh) 埋入式电力轨道
TWI550719B (zh) 半導體裝置與其形成方法
KR101795870B1 (ko) Fet 및 fet를 형성하는 방법
CN1287433C (zh) 三栅极器件的加工方法
CN101859770B (zh) 半导体结构及其形成方法
EP1804286A1 (en) Elongate nanostructure semiconductor device
TWI624932B (zh) 3d鰭式穿隧場效電晶體
KR20140099212A (ko) 맨드렐 산화 공정을 사용하여 finfet 반도체 디바이스용 핀들을 형성하는 방법
CN102301480A (zh) 纳米线网格器件及其制备方法
TW202042310A (zh) 具有標準單元的半導體元件及其製造方法
US11728411B2 (en) Stacked gate spacers
KR20230125772A (ko) 자기 정렬 격리부를 가지는 나노 와이어/시트 디바이스, 제조 방법 및 전자 기기
TW202105735A (zh) 半導體裝置
CN107026088A (zh) 半导体器件的制造方法
TWI710058B (zh) 積體單擴散阻斷
US10903331B2 (en) Positioning air-gap spacers in a transistor for improved control of parasitic capacitance
KR20020096654A (ko) 이중 게이트 mosfet 및 그 제조방법
CN105762187B (zh) 半导体器件及其制造方法
US20230402528A1 (en) Semiconductor Structures With Reduced Parasitic Capacitance And Methods For Forming The Same
WO2023070977A1 (zh) 半导体结构及其制造方法
US20230317858A1 (en) Interconnect structure for semiconductor device
US20230395679A1 (en) Multi-Gate Devices And Method Of Forming The Same
CN113410228B (zh) 多栅极的半导体结构及其制造方法
US20230187528A1 (en) Method for Forming a Precursor Semiconductor Device Structure

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant