CN101199042B - 一种集成电路 - Google Patents

一种集成电路 Download PDF

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CN101199042B
CN101199042B CN2006800218170A CN200680021817A CN101199042B CN 101199042 B CN101199042 B CN 101199042B CN 2006800218170 A CN2006800218170 A CN 2006800218170A CN 200680021817 A CN200680021817 A CN 200680021817A CN 101199042 B CN101199042 B CN 101199042B
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silicon
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hard mask
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CN101199042A (zh
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J·布拉斯克
J·卡瓦利罗斯
B·多勒
U·沙阿
S·达塔
A·马宗达
R·乔
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Intel Corp
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Abstract

描述了一种图案化半导体膜的方法。根据本发明的一个实施例，在具有全局晶体取向的半导体膜上形成硬掩模材料，其中半导体膜具有第一晶面和第二晶面，其中第一晶面比第二晶面密度高，并且其中硬掩模在第二晶面上形成。接着，将硬掩模和半导体膜图案化成硬掩模覆盖的半导体结构。然后，将硬掩模覆盖的半导体结构暴露于具有足以蚀刻第二晶面的化学强度但不具有足以蚀刻第一晶面的化学强度的湿法蚀刻过程。

Description

一种集成电路
发明背景 
1.技术领域
本发明涉及半导体处理领域，尤其涉及半导体结构及其制造方法。 
2.相关技术的讨论 
为了提高诸如微处理器之类的现代集成电路的性能，提出了绝缘体上的硅(SOI)晶体管。绝缘体上的硅(SOI)晶体管的优点在于它们能以全耗尽的方式工作。全耗尽晶体管的优点是具有优化导通电流/截止电流比的理想阈下梯度。所提出的能以全耗尽方式工作的SOI晶体管的例子是诸如图1所示的三栅晶体管100。三栅晶体管100包括在具有形成于单晶硅衬底105上的掩埋氧化物层103的绝缘衬底102上形成的硅体104。如图1所示，栅介电层106在硅体104的顶部和侧壁上形成。栅电极108在栅介电层上形成，并在三个侧面上围绕体104，实质上提供了具有三个栅电极(G1、G2、G3)的晶体管100：在硅体104的每一个侧壁上有一个栅电极，并在硅体104的顶面上有一个栅电极。如图1所示，源区110和漏区112在栅电极108相对两侧面上的硅体104中形成。有源沟道区是位于栅电极108之下且在源区110和漏区112之间的硅体区域。三栅晶体管100的优点在于它表现出良好的短通道效应(SCE)。三栅晶体管100表现出良好的短通道效应的一个原因是这种器件的非平面性使得栅电极108得以以在所有的三个侧面上围绕有源沟道区的方式设置。 
附图简述 
图1示出非平面即三栅晶体管。 
图2A-2E示出根据本发明的实施例形成半导体结构的方法。 
图2F是由图2E的结构形成的非平面晶体管的图示。 
图3A-3C示出根据本发明的实施例形成半导体结构的方法。 
图3D是利用图3C的半导体结构的非平面晶体管的图示。 
图4A-4C示出根据本发明的实施例形成半导体结构的方法。 
图4D是利用图4C的半导体结构的非平面晶体管的图示。 
图5是包括在一衬底上具有非平行方向的n型场效应晶体管和p型场效应晶体管的集成电路的一部分的图示。 
本发明的详细描述 
本发明的实施例描述了半导体结构和形成半导体结构的方法。在以下描述中，陈述了众多的细节，以提供对本发明的全面理解。在其它的例子中，为了不遮蔽本发明，没有特别详细地描述公知的半导体工艺和制造技术。 
本发明利用单晶半导体结构的原子层控制来使半导体器件的性能最佳化。在本发明的实施例中，将硬掩模覆盖的单晶结构暴露于各向异性湿法蚀刻剂中。该湿法蚀刻剂具有足以克服化学蚀刻反应的活化能势垒以便蚀刻半导体结构的低密度面的化学强度，但不具有足以克服化学蚀刻反应的活化能势垒的化学强度，从而不能蚀刻半导体结构的高密度面。通过选择适当的晶体取向、并通过在结构的低密度面上形成硬掩模、并通过使用具有适当的化学强度的湿法蚀刻化学性质，可形成具有期望的刻面、晶体取向和侧壁平滑度的半导体结构。在本发明的实施方式中，利用外延硅中的自然刻面来消除三维硅通道结构中的边缘粗糙度。在本发明的一个实施例中，利用自然刻面来形成可以很好地对沟道区进行栅控制的三维沟道结构。在本发明的其它实施例中，将PMOS和NMOS晶体管的半导体本体以特定排列形成于单晶半导体上，以利用该晶体取向并提高空穴和电子两者的迁移率。阅读以下的详细描述，将会清楚本发明的其它方面。 
根据本发明的实施方式，在图2A-2F中示出了利用自限制蚀刻和自然刻面形成三维半导体结构的方法。半导体结构的制造以衬底200开始。在本发明的一个实施例中，衬底200是绝缘体上的硅(SOI)衬底。SOI衬底200包括下面的单晶硅衬底202。诸如二氧化硅或氮化硅之类的绝缘层204在单晶衬底202上形成。单晶硅膜206在绝缘层204的上面形成。绝缘层204有时被称为“掩埋氧化物”层或“掩埋绝缘”层，且所形成的厚度足以将单晶硅膜206与下面的单晶硅衬底202隔离。在本发明的一个实施例中，绝缘层是厚度在200-2000埃的掩埋氧化物层。在本发明的一个实施例中，硅膜206是本征(即，未掺杂)硅外延膜。在其它的实施例中，将单晶硅膜206掺杂成p型或n型导电性，浓度水平在1×1016-1×1019原子/立方厘米之间。可原地掺杂硅膜206(即，沉积的同时掺杂)或在其形成于绝缘层204上之后通过例如离子注入法来掺杂。在沉积后掺杂硅膜206使n型器件和p型器件能够 在同一衬底上形成。在本发明的一个实施例中，所形成的硅膜的厚度约等于随后所形成的硅结构的期望高度。在本发明的一个实施例中，单晶硅膜206的厚度小于30纳米，并且理想地是约20纳米或更薄。 
绝缘体上的硅(SOI)衬底200能以任何公知的方法来形成。在一种称为SIMOX技术的绝缘体上的硅衬底的形成方法中，将氧原子以高剂量注入到单晶硅衬底中然后退火以在衬底内形成掩埋氧化物204。掩埋氧化物上的单晶硅衬底部分成为硅膜206。当前用于形成SOI衬底的另一种技术是一般称为“接合SOI”的外延硅膜转移技术。在该技术中，第一硅晶片具有生长在其表面上的稍后将在SOI结构中用作掩埋氧化物204的薄氧化物。接着，将高剂量的氢注入到第一硅晶片以在第一晶片的硅表面下形成应力区。然后将第一晶片翻转过来并接合到第二硅晶片的表面。然后将第一晶片沿由氢注入生成的高应力面劈开。劈开得到具有顶部的薄硅层和下面的掩埋氧化物的SOI结构，这些都在第二单结晶硅晶片的顶部上。诸如HCl平滑或化学机械抛光(CMP)之类的公知的平滑化技术可用于使硅膜206的顶部表面平滑至其期望的厚度。 
尽管将就形成于绝缘体上的硅(SOI)衬底上的硅结构来描述本发明，但本发明可在标准的单晶硅晶片或衬底上进行以形成“体”器件。硅结构可由单晶硅晶片直接形成或由形成于单晶硅衬底上的外延硅膜形成。另外，尽管是就单结晶硅结构的构造和由其形成的器件来说明本发明的实施例的，但本发明的方法和结构同样地适用于其它类型的半导体，诸如但不限于锗(Ge)、硅锗合金(SixGey)、砷化镓(GaAs)、锑化铟(InSb)、磷化镓(GaP)、以及锑化镓(GaSb)。因此，本发明的实施例包括半导体结构和利用诸如但不限于锗(Ge)、硅锗合金(SixGey)、砷化镓(GaAs)、锑化铟(InSb)、磷化镓(GaP)、以及锑化镓(GaSb)之类的半导体形成半导体结构的方法。 
在图2A中，单晶硅膜206具有如由 
Figure S2006800218170D00031
面限定的(100)全局晶体取向。具有(100)全局晶体取向的硅膜具有与膜的表面在同一平面上的<100>面。即，如图2A所示，具有(100)全局晶体取向的单结晶硅膜具有位于的 
Figure S2006800218170D00032
面中并具有z方向的法线轴的<100>面。 
在以下的描述中，用圆括号()来说明膜的全局晶体取向，如由 面限定并沿z方向，而用尖括号<>来描述在所述全局限定结晶膜内的具体局部平面。 
另外，如图2A所示，具有(100)晶体取向的单晶硅具有一对互相垂直的<110>面。即，(100)单晶硅具有位于 
Figure S2006800218170D00034
面中并具有沿y方向延伸的法线轴的<110>面，(100)单晶硅还具有位于 
Figure S2006800218170D00035
面中并具有沿x方向延伸的法线轴的<110>面。在本发明的一 个实施例中，将具有(100)全局晶体取向的硅膜206蚀刻以形成具有由<110>面形成的一对横向相对的侧壁以及与其垂直并位于<110>面中的第二对横向相对的侧壁的硅结构。 
为了将硅膜206蚀刻成硅体，可在硅膜206的顶部表面219上形成硬掩模材料208。硬掩模材料208是一种可提供用于硅膜206的蚀刻的硬掩模的材料。硬掩模材料208是一种能在硅膜206的蚀刻期间保持其外形(profile)的材料。硬掩模材料208是一种在硅膜206的蚀刻期间不被蚀刻或仅被轻微蚀刻的材料。在本发明的一个实施例中，硬掩模材料由这样一种材料形成，使得用于蚀刻硅膜206的蚀刻剂蚀刻硅膜206比蚀刻硬掩模材料快5倍且理想地至少快10倍。即，在本发明的一个实施例中，将硅膜和硬掩模选择为提供至少5∶1和理想地至少10∶1的蚀刻选择性。在本发明的一个实施例中，硬掩模材料208由氮化硅或氧氮化硅形成。在本发明的一个实施例中，硬掩模材料208由通过低压化学气相沉积(LPCVD)工艺形成的含有0-5％之间的碳的氮化硅膜形成。所形成的硬掩模材料208的厚度应足以在硅膜206的整个蚀刻期间维持其外形但不能厚到给图案化造成困难。在本发明的一个实施例中，所形成的硬掩模材料208的厚度为介于3纳米至50纳米之间，理想地是约10纳米。 
接着，如图2B所示，在硬掩模材料208上形成光刻胶掩模210。光刻胶掩模210包含将转移到硅膜206上的特征图案。光刻胶掩模210可由任何公知的技术形成，诸如通过均厚沉积光刻胶材料、然后掩蔽、曝光并显影光刻胶材料，成为具有用于硅膜206的期望的图案的光刻胶掩模210。光刻胶掩模210一般由有机化合物形成。所形成的光刻胶掩模210的厚度为在图案化硬掩模208的同时足以维持其外形、但又不至于厚到阻碍其光刻图案化至对于所采用的光刻系统和工艺所能够实现的最小的尺寸(即，关键尺寸)。在本发明的一个实施例中，光刻胶掩模210在单晶硅膜206上的定向应限定出一个具有与<110>晶面对齐的一对横向相对的侧壁和与该第一对与<110>面对齐的侧壁垂直的第二对横向相对侧壁的光刻胶掩模。 
接着，如图2C所示，与光刻胶掩模210对齐地蚀刻硬掩模材料208以形成如图2C所示的硬掩模212。光刻胶掩模210防止硬掩模材料208的下面的部分被蚀刻。在本发明的一个实施例中，用可蚀刻硬掩模材料但不蚀刻下面的硅膜206的蚀刻剂蚀刻硬掩模材料208。在本发明的一个实施例中，用对下面的硅膜206具有几乎完美的选择性的蚀刻剂蚀刻硬掩模材料。即，在本发明的一个实施例中，硬掩模蚀刻剂蚀刻硬掩模材料208比蚀刻下面的硅膜206至少快20倍(即，蚀刻剂具有至 少20∶1的硬掩模-硅膜选择性)。当硬掩模材料208是氮化硅或氧氮化硅膜时，可利用诸如反应离子蚀刻之类的干法蚀刻工艺将硬掩模材料208蚀刻成硬掩模212。在本发明的一个实施例中，利用包括CHF3、O2和Ar的化学物质反应离子蚀刻氮化硅或氧氮化硅硬掩膜。 
接着，如图2C所示，在将硬掩模薄膜208图案化成硬掩模212后，可通过公知的技术去除光刻胶掩模210。例如，可利用包括硫酸和过氧化氢的“piranha(食人鱼)”清洗溶液去除光刻胶掩模210。此外，来自光刻胶掩模210的残余可利用O2灰化来去除。 
尽管并非必需，但期望的是在图案化硅膜206之前去除光刻胶掩模210，使得来自光刻胶的聚合物膜不在图案化硅膜206的侧壁上形成。例如，当硅膜206用作非平面器件的半导体本体或凸凌时，期望的是在蚀刻硅膜之前首先去除光刻胶掩模，因为干法蚀刻工艺可腐蚀光刻胶掩模并导致在硅体的侧壁上生长聚合物膜，该聚合物膜难以去除且会不利地影响器件性能。 
接着，如图2D所示，与硬掩模212对齐地蚀刻硅膜206以形成具有与<110>晶面对齐的第一对横向相对侧壁218和与<110>晶面对齐的第二对横向相对侧壁220的图案化硅膜214。硬掩模212防止在蚀刻工艺期间硅膜206的下面的部分被蚀刻。在本发明的一个实施例中，蚀刻持续到到达下面的掩埋氧化物层204。用在不显著蚀刻硬掩模212的情况下蚀刻硅膜206的蚀刻剂蚀刻硅膜206。在本发明的一个实施例中，用蚀刻硅膜206的速率比蚀刻硬掩模212的速率快5倍，理想地快10倍的蚀刻剂蚀刻硅膜206(即，蚀刻剂对硅膜206与硬掩模212的蚀刻选择性至少是5∶1，理想地至少是10∶1)。可利用任何适当的工艺来蚀刻硅膜206。在本发明的一个实施例中，各向异性地蚀刻硅膜206使得硅体214具有与硬掩模212的侧壁对齐地形成的几乎垂直的侧壁218。当硬掩模212是氮化硅或氧氮化硅膜时，可利用诸如反应离子蚀刻(RIE)或具有包括Cl2和HBr的化学物质的等离子体蚀刻之类的干法蚀刻工艺来蚀刻。 
在蚀刻硅膜206形成硅体或结构214后，侧壁218一般将具有约2-4纳米的线边缘粗糙度222。当形成具有仅20-30纳米的侧壁218之间的宽度的硅体或结构时，这一表面粗糙度大得不可接受，会不利地影响器件性能。 
因此，在本发明的一个实施例中，在硬掩模212存在于结构214上的时候将硅结构214暴露于湿法蚀刻或“刻面”蚀刻，以去除边缘粗糙度和/或修整该结构的形状以增强器件性能。在本发明的一个实施例中，将覆盖了硬掩模212的硅结构 214暴露于各向异性湿法蚀刻剂中。湿法蚀刻剂具有足以克服化学蚀刻反应的活化能势垒以便蚀刻半导体结构的低密度面的化学强度，但不具有足以克服化学蚀刻反应的活化能势垒的化学强度，从而不能蚀刻密度大的面。 
在本发明的一个实施例中，使用可蚀刻较低密度的<100>和<110>面但不能蚀刻较高密度的<111>面湿法蚀刻化学物质和工艺。因为硬掩模212覆盖硅结构214的顶部表面上的低密度<100>面，所以所述较低密度的面被保护免受蚀刻。因为顶部表面上的较低密度面<100>被遮蔽并且因为蚀刻剂不具有足以蚀刻<111>面的化学强度，所以湿法蚀刻停止在第一完全完整或邻接的<111>面上，如图2E所示。由此，“刻面”或湿法蚀刻是自限制的。因此，依据湿法蚀刻的自我限制，仅<111>面和用于屏蔽较小密度的<110>和<100>面的抗蚀膜维持暴露。本发明的刻面蚀刻可被称为各向异性蚀刻，因为它在一个方向上以一种速率蚀刻而在其它方向上以第二较慢的速率蚀刻或根本不蚀刻。因为蚀刻工艺蚀刻<100>和<110>面但不蚀刻<111>面，所以如图2E所示刻面或湿法蚀刻形成具有由<111>面限定的侧壁232的硅结构。各向异性湿法蚀刻从侧壁218去除表面粗糙度222(图2D)并生成如图2E所示的光学意义上平滑的侧壁232。此外，在将结构214暴露于刻面蚀刻足够长的时间后，侧壁218由<111>面限定并生成具有V形或内锥形侧壁232的结构230。侧壁232以62.5度的角度α从结构230的顶面219向内形成角度。在本发明的一个实施例中，结构230的顶面219在横向相对侧壁232之间的宽度(W1)介于20-30nm，而底面在横向相对侧壁之间的宽度(W2)为10-15nm。 
在本发明的一个实施例中，湿法蚀刻或“刻面”蚀刻是基于氢氧化物的蚀刻，其具有足够低的氢氧化物浓度和亲核性(即，化学强度)，使得不存在完全完整的<111>面的蚀刻。在本发明的一个实施例中，将结构214暴露于包含小于1％体积的氢氧化氨(NH4OH)的刻面或湿法蚀刻剂中。在本发明的一个实施例中，将结构214在5-25℃温度范围内暴露于包括0.2-1％体积的NH4OH湿法蚀刻剂中。在本发明的一个实施例中，在刻面蚀刻期间将介于600-800千赫频率范围、消散介于0.5-3瓦/cm2之间的声能施加到蚀刻溶液中。在本发明的一个实施例中，将覆盖硬掩模的硅结构暴露于刻面蚀刻15秒至5分钟。 
在本发明的一个实施例中，刻面或湿法蚀刻可包含氢氧化四烷基胺(例如，介于5-20℃温度之间的氢氧化四乙铵和氢氧化四甲铵)的超稀(＜0.1％体积)水溶液。 
所制造的硅结构230可用于制造诸如晶体管和电容器之类的半导体器件以及微机电系统(MEMS)和光电器件。在本发明的一个实施例中。半导体结构230用作 用于非平面或三维晶体管的半导体本体或凸凌，诸如但不限于三栅晶体管、双栅晶体管、FINFET、Ω-FET或π-FET。 
在本发明的一个实施例中，硅结构230提供用于图2F所示的三栅晶体管240的硅体或凸凌。为了制造如图2F所示的三栅晶体管240，从硅结构230去除硬掩模212。在本发明的一个实施例中，当硬掩模212是氮化硅或氧氮化硅膜时，包含磷酸去离子水液的湿法蚀刻剂可用于去除硬掩模。在本发明的一个实施例中，硬掩模蚀刻剂包括加热到150-170℃、理想地是160℃的80-90体积％之间的磷酸水溶液。在本发明的一个实施例中，在去除硬掩模212后，可利用标准SC1和SC2清洗来清洗衬底。必须是在用磷酸去除硬掩模后清洗衬底，因为磷酸一般包括很多可影响器件性能或可靠性的金属杂质。应意识到如果期望形成FINFET或双栅器件，则硬掩模212应留在硅结构230上以隔离半导体结构230的顶部表面，以免由随后形成的栅电极控制。 
接着，在侧壁232上以及半导体本体230的顶部表面上形成栅介电层250。栅介电层250可以是任何公知且适当的栅介电层，诸如但不限于二氧化硅或氮化硅栅介电层。另外，栅介电层250可以是高k栅介电层，诸如但不限于氧化铪、氧化锆、氧化钛和氧化钽。诸如但不限于化学气相沉积和原子层沉积之类的任何公知的技术可用于形成栅介电层250。 
接着，如图2F所示，在半导体结构230的顶部表面和侧壁上的栅介电层250上形成栅电极260。垂直于侧壁232形成栅电极260。栅电极可由任何公知的栅电极材料形成，诸如但不限于掺杂的多晶硅以及诸如但不限于钨、钽、钛及其氮化物等金属膜。另外，应意识到栅电极不一定是单一品种的材料，可以是薄膜的复合层叠，诸如但不限于形成于栅介电层上的顶部有多晶硅膜的下层金属膜。栅介电层和栅电极可通过均厚沉积法或在半导体本体上生长栅介电层然后在栅介电层上均厚沉积栅电极材料来形成。然后可利用公知的光刻和蚀刻技术来图案化栅介电层和栅电极材料以形成栅电极260和栅介电层250，如图2F所示。或者，栅介电层和栅电极可利用公知的替换栅工艺来形成。如图2F所示，在栅电极260的相对侧面上的硅体230中形成源区272和漏区274。诸如固体源扩散或离子注入之类的任何公知的适当技术可用于形成源区和漏区。在本发明的一个实施例中，所形成的源区272和漏区274的浓度是1×1019-1×1021原子/立方厘米。 
所制造的非平面晶体管240包括如图2F所示由栅介电层250和栅电极260围绕的半导体本体230。位于栅电介质和栅电极下的半导体230的部分是器件的沟道 区。在本发明的一个实施例中，将源区和漏区掺杂成第一导电类型(n型或p型)而将沟道区掺杂成第二相对的导电类型(p型或n型)或不掺杂。当导电沟道通过栅电极260在硅体230的沟道区中形成时，电荷(即，空穴和电子)在源区和漏区之间沿硅体230的<110>面流动。即，在晶体管240中，电荷迁移沿结构240中的<110>晶面进行。研究发现，沿<110>方向的电荷迁移提供良好的空穴迁移率。因此，在本发明的一个实施例中，器件240是p型器件，其中源区和漏区形成为p型导电性并且载流子是空穴。另外，通过使硅体230的侧壁向内减小，栅电极260对体230的沟道区具有良好的控制，实现晶体管240的快速“导通”和“截止”。 
图3A-3D示出根据本发明的另一个实施例形成单晶硅体或结构的方法。如图3A所示，在具有(100)全局晶体取向的单晶硅膜306上形成硬掩模312。可如上所述地形成硬掩模312。然而，在图3A中，硬掩模312在硅膜306上的定向形成了与<100>面对齐的一对侧壁和同样与<100>面对齐的第二对侧壁。(应意识到硬掩模312的方向在 
Figure S2006800218170D00081
面上从图2A所示的硬掩模212的方向旋转了约45度。) 
接着，如图3B所示，与硬掩模312对齐地蚀刻(100)全局晶体取向的硅膜306以形成具有与<100>面对齐的一对横向相对侧壁318以及与第一对垂直并同样与<100>面对齐的第二对侧壁320的硅结构314。可如上所述地蚀刻硅膜306。 
接着，在硬掩模312存在于硅结构314的顶面319上时，将硅结构314暴露于刻面湿法蚀刻剂中。刻面湿法蚀刻剂具有足以蚀刻低密度的<110>和<100>面的化学强度但不具有足以蚀刻高密度的<111>面的强度。因为硅结构314的顶部表面319上的低密度<100>面由硬掩模312覆盖并且因为蚀刻剂不具有足以蚀刻高密度的<111>面的化学强度，所以硅结构314转变成如图3C所示的具有由相交的<111>面形成的“V”切口形状的一对侧壁332的硅结构330。如前所述，刻面蚀刻是自我限制性的，并在第一邻接的<111>面处停止。侧壁332的<111>面以约55度的角β相交。晶体取向、原子屏蔽以及良好控制的各向异性湿法蚀刻剂的组合实现了具有“V”切口侧壁332的硅结构330的形成。 
如上所述，硅结构330可用于形成硅非平面或三维器件以及微机器和MEMS器件。在本发明的一个实施例中，硅结构330用于形成诸如如图3D所示的三栅晶体管330之类的非平面晶体管。如图3D所示，垂直于侧壁332形成栅电极360。如图3D所示，非平面器件具有形成于硅体330的一部分年上或周围的栅介电层350和栅电极360。源区372和漏区374在栅电极的相对侧上的硅体330中形成。晶体管340中从源区至漏区的电荷迁移平行于或沿<100>面。因为电荷迁移沿<100>面 进行，所以硅结构330提供良好的电子迁移率，因此可完美地用于载流子是电子且源区372和漏区374是n型导电性的n型场效应晶体管(NFET)的制造。 
图4A-4D示出根据本发明的另一个实施例形成半导体本体或结构的方法。如图4A所示，提供了诸如绝缘体上的硅(SOI)衬底之类的包括下部的单晶硅衬底402、掩埋氧化物层404和单晶硅膜406的衬底400。尽管理想的是采用绝缘体上的硅衬底400，但如上所述可使用其它公知的半导体衬底。在本发明的一个实施例中，如图4A所示单晶硅膜406具有(110)全局晶体取向。具有(110)全局晶体取向的单晶硅膜具有与膜表面在同一个平面上或平行于膜的表面的硅晶格的<110>面。即，如图4A所示，具有(110)全局晶体取向的单晶硅膜是 
Figure S2006800218170D00091
面中的<110>面，具有沿z方向的法线轴。另外，具有(110)全局晶体取向的单晶硅膜具有垂直于<110>面并互相垂直的<111>面和<110>面。即，如图4A所示，在具有(110)全局晶体取向的单晶硅膜406中存在着处于 
Figure S2006800218170D00092
面中并具有沿y方向的法线轴的<111>面，也存在着处于 
Figure S2006800218170D00093
面中并具有沿x方向的法线轴的<110>面。接着，如图4A所示，如上所述地在具有(110)晶体取向的单晶硅膜406上形成硬掩模412。硬掩模412在硅膜406上定向以形成与<110>面对齐的一对侧壁和与<111>面对齐的第二对垂直侧壁。硬掩模412可由上述的材料和方法形成。 
接着，如图4B所示，与硬掩模412对齐地蚀刻(100)硅膜以形成具有与<110>面对齐或平行于<110>面的一对横向相对侧壁418以及与第一对418垂直并与<111>面对齐或平行于<111>面的第二对侧壁420的硅结构414。然后将覆盖硬掩模412的硅结构414暴露于刻面湿法蚀刻剂。刻面湿法蚀刻剂具有足以蚀刻密度较低的<110>面的化学强度但不具有足以蚀刻高密度的<111>面的化学强度。因为的顶部表面419上的低密度的<100>面由硬掩模412覆盖并且因为蚀刻剂不具有足以蚀刻高密度的<111>面的化学强度，所以结构414转变成如图4C所示的具有由<111>面限定的一对横向相对侧壁432的结构430。在将结构414暴露于刻面蚀刻剂足够长的时间后，侧壁432由<111>面限定并生成具有V形或内锥形侧壁的结构。侧壁432以约62.5度的角度γ从结构430的顶面419向内形成角度。在本发明的一个实施例中，顶面419在横向相对侧壁432之间的宽度(W1)介于20-30nm，而底面在横向相对侧壁440之间的宽度(W2)为10-15nm。晶体取向、硬掩模屏蔽以及具有适当的化学强度的湿法蚀刻剂的组合实现了内锥形侧壁432的硅结构430的形成。 
如上所述，硅结构430可用于形成诸如硅非平面或三维器件之类的各种公知的半导体器件以及光电子器件和MEMS器件。在本发明的一个实施例中，如图4D 所示，硅结构430被用于形成诸如三栅晶体管440之类的非平面晶体管。如图4D所示，三栅晶体管440具有形成于硅体430的一部分之上及周围的栅介电层450和栅电极460。如图4D所示，栅电极460在垂直于侧壁432的方向上延伸。栅介电层450和栅电极460可由如上所述的任何适当的材料和适当的已知方法来形成。如图4D所示，源区472和漏区474在栅电极460的相对侧上的硅体430中形成。硅体430中从源区472至漏区474的电荷迁移平行于或沿<110>面进行。硅体430的内锥形侧壁432提供了对器件的沟道区的良好栅控制460，这实现了器件440的快速“导通”和“截止”。 
尽管迄今为止对本发明的描述是参考利用晶向、硬掩模屏蔽以及良好控制的湿法蚀刻剂的组合的单结晶硅结构的成形或“刻面”了本发明，但本发明的概念同样适用于其它类型的单晶半导体膜，诸如但不限于锗(Ge)、硅锗合金(SixGey)、砷化镓(GaAs)、锑化铟(InSb)、磷化镓(GaP)、以及锑化镓(GaSb)。例如，单晶锑化铟(InSb)结构可在5-15℃范围的温度下利用包含0.05-0.1mol/L柠檬酸的水溶液的湿法蚀刻剂进行刻面处理。类似地，单晶砷化镓(GaAs)结构可通过将覆盖硬掩模的砷化镓结构在5-15℃范围的温度下暴露于小于0.05mol/L的柠檬酸水溶液进行刻面处理。 
另外，在本发明的一个实施例中，由p型晶体管和n型晶体管520形成集成电路，使这些晶体管定向或成形以优化每一种类型的晶体管的性能。例如，如图5所示，在本发明的一个实施例中，如参考图2A-2F所述图案化具有(110)全局晶体取向的单晶硅膜，以形成用于p型非平面晶体管510的硅体512，其中电荷(空穴)迁移平行于<110>面，并且还如参考图3A-3D所述图案化具有(110)全局晶体取向的单晶硅膜，以形成用于n型非平面晶体管520的硅体522，其中电荷(电子)迁移平行于<100>面。因此，p型非平面晶体管和n型非平面晶体管在衬底上以彼此不平行(例如，偏离45度)的方式定向，以优化p型晶体管的空穴迁移率和n型非平面晶体管的电子迁移率。在本发明的其它实施例中，p型器件和n型器件的半导体本体相对于彼此的定向使得刻面蚀刻剂可以使体的形状成为优化每一种器件类型的性能的结构。由此，可大大提高包括n型非平面晶体管和p型非平面晶体管的集成电路的性能。 

Claims (5)

1.一种集成电路，包括：
具有第一半导体本体的第一非平面晶体管，其中所述第一半导体本体中的电荷迁移沿第一方向；以及
具有第二半导体本体的第二非平面晶体管，其中所述第二半导体本体中的电荷迁移沿第二方向，其中所述第二方向不与所述第一方向平行，
其中，所述第一半导体本体和所述第二半导体本体由单晶硅膜形成，并且
所述单晶硅膜是通过一种包括如下步骤的方法进行图案化的：
在单晶硅膜上形成硬掩模；
与所述硬掩模对齐地蚀刻所述单晶硅膜以形成具有顶部表面和一对横向相对侧壁的单晶硅结构，所述单晶硅结构被所述硬掩模覆盖；以及
将所述硬掩模覆盖的所述单晶硅结构暴露于包括水和小于1％体积的NH4OH的湿法化学蚀刻剂中以蚀刻掉所述单晶硅结构的一部分，其中所述湿法化学蚀刻剂是自限制性的，使得它在所述单晶硅结构的第一完全完整的<111>晶面上停止。
2.如权利要求1所述的集成电路，其特征在于，所述第一方向相对于所述第二方向成45度。
3.如权利要求1所述的集成电路，其特征在于，所述第一非平面晶体管是n型场效应晶体管，所述第一方向平行于所述第一半导体本体的所述单晶硅膜的<100>面。
4.如权利要求1所述的集成电路，其特征在于，所述第二非平面晶体管是p型场效应晶体管，所述第二方向平行于所述第二半导体本体的所述单晶硅膜的<110>面。
5.如权利要求1所述的集成电路，其特征在于，所述第二非平面晶体管是p型场效应晶体管，所述第二方向平行于所述第二半导体本体的所述单晶硅膜的<110>面，所述第一非平面晶体管是n型场效应晶体管，所述第一方向平行于所述第一半导体本体的所述单晶硅膜的<100>面。
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US8581258B2 (en) 2013-11-12
US20120032237A1 (en) 2012-02-09
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