CN101032032A - 具有变细的下本体部分的非平面器件及制造方法 - Google Patents

具有变细的下本体部分的非平面器件及制造方法 Download PDF

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CN101032032A
CN101032032A CNA200580033161XA CN200580033161A CN101032032A CN 101032032 A CN101032032 A CN 101032032A CN A200580033161X A CNA200580033161X A CN A200580033161XA CN 200580033161 A CN200580033161 A CN 200580033161A CN 101032032 A CN101032032 A CN 101032032A
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semiconductor body
sidewall
described semiconductor
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CN100481514C (zh
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乌黛·沙阿
布赖恩·多伊尔
贾斯廷·布拉斯克
罗伯特·召
托马斯·莱特森
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Intel Corp
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Abstract

一种非平面半导体器件具有形成在衬底的绝缘层上的半导体本体。半导体本体具有与形成在绝缘层上的底表面相对的顶表面和一对横向相对的侧壁，其中在顶表面处的横向相对的侧壁之间的距离大于在底表面处的横向相对的侧壁之间的距离。在半导体本体的顶表面和半导体本体的侧壁上形成栅介质层。在半导体本体的顶表面和侧壁上的栅介质层上形成栅电极。在半导体本体中、在栅电极的相对侧上形成一对源极/漏极区。

Description

具有变细的下本体部分的非平面器件及制造方法
技术领域
本发明涉及半导体器件领域，尤其涉及一种具有变细的下本体部分的非平面三栅极晶体管以及制造方法。
背景技术
为了提高现代集成电路例如微处理器的性能，已经提出绝缘体上硅(SOI)晶体管。绝缘体上硅(SOI)晶体管具有如下优点：它们能以全耗尽方式工作。全耗尽型晶体管对于最佳ON电流/OFF电流比具有理想的亚阈值梯度的优点。
所提出的能以全耗尽方式工作的SOI晶体管的例子是如图1所示的三栅极晶体管100。三栅极晶体管100包括形成在绝缘衬底102上的硅本体104，该绝缘衬底102具有形成在单晶硅衬底105上的掩埋氧化物层103。如图1所示，栅介质层106形成在硅本体104的顶部和侧壁上。栅电极108形成在栅介质层上并在三个侧面环绕本体104，基本上提供具有三个栅电极(G1、G2、G3)的晶体管100，在硅本体104的每一个侧壁上有一个栅电极，在硅本体104的顶表面上有一个栅电极。如图1所示，源极区110和漏极区112形成在硅本体104中且位于栅电极108的相对侧上。
三栅极晶体管100的优势在于它呈现出良好的短沟道效应(SCE)。三栅极晶体管100获得良好的短沟道效应的一个原因是器件的非平面化使得以环绕有源沟道区的方式设置栅电极108。即，在三栅极器件中，栅电极108与沟道区的三个侧面接触。不幸的是，第四侧面，沟道的底部通过掩埋氧化物层103与栅电极绝缘，并由此不在邻近栅极的控制下。
附图说明
图1是非平面或三栅极器件的示图；
图2A和2B示出根据本发明的具有变细的下本体部分的三栅极或非平面器件；
图3A示出具有多个变细的下本体部分的非平面器件；
图3B是具有变细的下本体部分并包括侧壁隔离物、源极/漏极延伸区和硅化物源极/漏极区的示图；
图4A-4H示出形成根据本发明的实施例的具有变细的下本体部分的非平面器件的方法；
图5A-5D示出本发明的实施例，外形蚀刻可以使下本体部分变细。
具体实施方式
本发明是一种新颖的具有变细的下本体部分的非平面器件及其制造方法。在下面的说明中，为了更彻底地理解本发明，阐述了很多具体细节。在其它的实例中，为了不必要地使本发明晦涩难懂，没有特别详细地描述公知的半导体工艺和制造技术。
本发明的实施例包括具有半导体本体的非平面或三栅极晶体管，所述半导体本体通过栅介质层和栅电极环绕在三个侧面上。在本发明的实施例中，使半导体本体的底部比半导体本体的顶部更细。使半导体本体的底部比顶部更细提高了本体底部上的栅极控制，从而获得了更好的短沟道效应。在本发明的实施例中，利用干法蚀刻工艺将半导体膜蚀刻成半导体本体，所述干法蚀刻工艺使用第一处理气体化学物质和第一RF偏置(RF bias)。在形成半导体本体之后，使用相同的蚀刻化学物质和设备但是使用更低的偏压使本体的下部分变细，以便使下本体部分向内逐渐变细或对其进行刻面(facet)。
图2A和2B示出具有下本体部分变细的半导体本体的非平面或三栅极器件200。图2A是晶体管200的俯视/侧视图，而图2B是通过栅电极截取的截面图。晶体管200形成在衬底202上并包括半导体本体或鳍204。栅介质层206形成在半导体本体204的顶表面234以及侧壁230和232上。栅电极208形成在栅介质层206上并在三个侧面上环绕半导体本体或鳍。如图2A所示，源极区210和漏极区212形成在半导体本体中且位于栅电极208的相对侧上。
如图2A和2B已经明显地示出，半导体本体204具有比顶部224更细的底部222。也就是，在顶表面234处的侧壁230和232之间的距离大于在底表面236处的侧壁230和232之间的距离。在本发明的实施例中，顶部224的侧壁230和232基本上垂直并且分开相同的距离，而对底部222的侧壁230和232进行刻面或使其向内逐渐变细，以减少在底部中的侧壁230和232之间的距离。在本发明的实施例中，底表面附近的侧壁230和232之间的距离是顶表面234附近的侧壁230和232之间的距离的1/2到2/3之间。在本发明的实施例中，侧壁230和232大约在半导体本体204的高度238的中点处开始向内部逐渐变细(即侧壁在顶表面234和底表面236之间的中点处开始向内逐渐变细)。在本发明的实施例中，在顶表面234处的侧壁230和232之间的距离在20-30纳米之间，而底表面236附近的侧壁230和232间的距离在10-15纳米之间。在本发明的实施例中，使半导体本体204的底部222足够细以便使底部的栅极控制与顶部的栅极控制相似。在本发明的实施例中，使半导体本体204的底部222相对于顶部足够细以改善晶体管200的短沟道效应。
另外，如图5A-5D所示，可以使用其它的半导体本体轮廓或形状以改善三栅极或非平面晶体管200的短沟道效应(SCE)。例如，如图5A所示，半导体本体204可以具有一对侧壁230和232，它们从顶表面234到底表面236向内连续地变细。另外，在本发明的实施例中，如图5B所示，半导体本体204可以具有侧壁230和232，它们从顶表面到底表面向内连续地变细，并且在一点或基本在点502处到达底表面236。在本发明的另一实施例中，如图5C所示，半导体本体204可以具有一对侧壁230和232，它们包括由相同距离分开的上部垂直部分510，中间向内逐渐变细的部分512，以及由第二距离分开的垂直侧壁的下部分514，该第二距离小于分开顶部侧壁510的距离。在本发明的另一实施例中，半导体本体可以具有其中侧壁230和232被刻面或向内逐渐变细的上部分224，以及其中侧壁230和232是垂直的或基本垂直的底部222。在图5A-5D所示的每一个例子中，在顶表面上的半导体本体204的侧壁230和232之间的距离大于底表面上的半导体本体间的距离。通过这种方式，栅电极208可以对底表面处的半导体本体有更好的控制并且由此改善器件的短沟道效应。
在本发明的实施例中，三栅极晶体管200形成在绝缘衬底202上，该绝缘衬底包括下单晶硅衬底250，在其上形成有绝缘层252，例如二氧化硅膜。在本发明的实施例中，绝缘层252是SOI衬底的掩埋氧化物层。然而，三栅极晶体管200可以形成在任何公知的绝缘衬底上，例如由二氧化硅、氮化物、氧化物和蓝宝石形成的衬底。
半导体本体204形成在绝缘衬底202的绝缘层252上。半导体本体204可以形成在任何公知的材料上，例如但不限于硅(Si)、锗(Ge)、硅锗(SixGey)、砷化镓(GaAs)、InSb、GaP和GaSb。半导体本体204可以由任何公知的通过施加外部电控制可从绝缘状态反向变换到导电状态的材料形成。当希望晶体管200具有最好的电性能时，半导体本体204在理想情况下为单晶膜。例如，当晶体管200用于高性能应用，例如诸如微处理器的高密度电路时，半导体本体204是单晶膜。然而，当晶体管200用于对性能的要求不是很严格的应用时，例如用于液晶显示器时，半导体本体204可以是多晶膜。绝缘体252使半导体本体204与单晶硅衬底250绝缘。在本发明的实施例中，半导体本体204是单晶硅膜。
栅介质层206形成在半导体本体204上并环绕半导体本体204的三个侧面，如图2A和2B所示。栅介质层206形成在侧壁230上或邻近于侧壁230，形成在本体204的顶表面234上，以及形成在本体204的侧壁232上或邻近于侧壁232，如图2A和2B所示。栅介质层206可以是任何公知的栅介质层。在本发明的实施例中，栅介质层是二氧化硅(SiO2)，氮氧化硅(SiOxNy)或氮化硅(Si3N4)介质层。在本发明的实施例中，栅介质层206是形成为厚度在5-20之间的氮氧化硅膜。在本发明的实施例中，栅介质层206是诸如金属氧化物电介质的高k栅介质层，例如但不限于五氧化钽(TaO5)，氧化钛(TiO2)和氧化铪(HfO)。栅介质层206可以是其它类型的高k介质层，例如但不限于PZT和BST。
如图2A和2B所示，栅电极208形成在栅介质层206上并环绕栅介质层206。栅电极208形成在于半导体本体204的侧壁230上形成的栅介质层206上或与其邻近，形成在于半导体本体204的顶表面34上形成的栅介质层206上，以及形成在于半导体本体204的侧壁232上形成的栅介质层206上或与其邻近。栅电极208具有一对横向相对的侧壁260和262，它们由定义晶体管200的栅长(Lg)的距离分开。在本发明的实施例中，栅电极208的横向相对的侧壁260和262沿着垂直于半导体本体204的侧壁230和232的方向延伸。
栅电极208可以由任何适当的栅电极材料形成。在本发明的实施例中，栅电极208包括掺杂浓度介于1×1019原子/cm3到1×1020原子/cm3之间的多晶硅膜。在本发明的实施例中，栅电极可以是金属栅电极，例如但不限于钨、钽、钛和它们的氮化物。在本发明的实施例中，栅电极由中间间隙功函数(midgap workfunction)介于4.5到4.8eV之间的材料形成。应当了解栅电极208不必是单一材料并且可以是薄膜的组合叠层，例如但不限于多晶硅/金属电极或金属/多晶硅电极。
晶体管200具有源极区210和漏极区212。源极区210和漏极区212形成在半导体204中且位于栅电极208的相对侧上，如图2A所示。当形成NMOS晶体管时，源极区210和漏极区212形成为n型导电类型，当形成PMOS器件时形成为p型导电性。在本发明的实施例中，源极区210和漏极区212具有介于1×1019原子/cm3到1×1021原子/cm3之间的掺杂浓度。源极区210和漏极区212可以由相同的浓度形成或者可以包括具有不同浓度或掺杂剂分布的子区，例如顶部区域(例如源极/漏极延伸区)和接触区域。在本发明的实施例中，当晶体管200是对称晶体管时，源极区210和漏极区212具有相同的掺杂浓度和分布。在本发明的实施例中，当晶体管200形成为不对称晶体管时，源极区210和漏极区212的掺杂浓度分布可以变化以便实现本领域公知的任意特殊的电特性。源极区210和漏极区212可以共同地被称为源极/漏极区对。
位于源极区210和漏极区212之间的半导体本体204的部分限定晶体管200的沟道区270。还可以将沟道区270限定为由栅电极208环绕的半导体本体204的区域。然而有时，源极/漏极区可以通过例如扩散稍微地延伸到栅电极的下方以限定比栅电极长度(Lg)略小的沟道区。在本发明的实施例中，沟道区270是本征或未掺杂的单晶硅。在本发明的实施例中，沟道区270是掺杂的单晶硅。当沟道区270被掺杂时，通常将其掺杂到导电率的水平介于1×1016原子/cm3到1×1019原子/cm3之间。在本发明的实施例中，当掺杂沟道区时，通常将其掺杂为具有与源极区210和漏极区212相反的导电类型。例如，当源极和漏极区是n型导电性时，沟道区将被掺杂为p型导电性。类似地，当源极和漏极区是p型导电性时，沟道区将是n型导电性。通过这种方式，三栅极晶体管200可以分别形成为NMOS晶体管或PMOS晶体管。沟道区270可以被均匀地掺杂，或者可以被非均匀地掺杂，或者具有不同的浓度以提供特殊的电特性和性能特性。例如，如果需要，沟道区270可以包括公知的“光晕”区。
通过提供在三个侧面环绕半导体本体的栅电极以及栅电介质，三栅极晶体管的特征在于：具有三个沟道和三个栅极，在硅本体204的侧面230上的源极和漏极区之间延伸的一个栅极和沟道(G1)，在硅本体204的顶表面上的源极和漏极区之间延伸的第二栅极和沟道(G2)，并且在硅本体204的侧壁上的源极和漏极区之间延伸的第三栅极和沟道(G3)。晶体管200的栅极“宽度”(Gw)是三个沟道区的宽度的总和。也就是，晶体管200的栅极宽度等于硅本体204的侧壁230的长度，加上硅本体204的顶表面234的长度，加上硅本体204的侧壁232的长度。较大“宽度”的晶体管可以通过使用耦合到一起的多个器件(例如，由单个栅电极208环绕的多个硅本体204)来获得，如图3A所示。
因为由栅电极208和栅电介质206在三个侧面环绕沟道区270，晶体管200可以以完全耗尽的方式工作，其中当使晶体管200“导通”时，沟道区270完全耗尽由此提供全耗尽晶体管的有利的电特性和性能。也就是，当使晶体管200“导通”时，在沟道区270中与区270的表面处的反型层一起形成耗尽区(即反型层形成在半导体本体的侧表面和顶表面上)。反型层具有与源极和漏极区相同的导电类型并在源极和漏极区之间形成导电沟道以允许电流在其间流过。耗尽区耗尽了来自反型层下方的自由载流子。耗尽区延伸到沟道区270的底部，因此晶体管可以被称为“全耗尽”晶体管。在本发明的实施例中，半导体本体204的下部分222相对于上部分变得更细，以使栅电极可以更好地控制半导体本体的下部分。通过使下部分变细，两个侧壁栅极G1和G3可以更容易地耗尽来自反型层下方的自由载流子，所述反型层形成在半导体本体204的下部分的侧壁上。通过使半导体本体204的下部分222变细，来自侧壁的两个栅极G1和G3可以以与三个栅极G1、G2和G3控制半导体本体204的上部分224中的沟道的方式相类似的方式控制沟道区。使本体或鳍的底部变细不仅减少两个栅极之间的半导体的厚度，而且减少本体与掩埋氧化物接触的部分的宽度。这些组合的效应减少了具有变细的下本体部分的三栅极器件中的短沟道效应。
因为在半导体本体204中的水平和垂直方向上形成沟道270的反型层，所以本发明的晶体管200可以被称为非平面晶体管。因为从水平(G2)和垂直侧面(G1和G3)施加来自栅电极208的电场，所以本发明的半导体器件也可以被认为是非平面器件。
如上所述，晶体管200的栅极宽度等于从晶体管200的半导体本体204产生的三个栅极宽度的总和。为了制造具有更大的栅极宽度的晶体管，晶体管200可以包括附加的或多个半导体本体或鳍204，如图3A所示。每一个半导体本体或鳍204具有形成在其顶表面和侧壁上的栅介质层206，如图3A所示。栅电极208形成在每一个半导体本体204上的每一个栅介质层206上或与其邻近。每一个半导体本体204包括形成在半导体本体204中的、位于栅电极208的相对侧上的源极区210和漏极区212，如图3A所示。在本发明的实施例中，每一个半导体本体208形成为其宽度和高度(厚度)与其它半导体本体204相同。在本发明的实施例中，半导体本体204的每一个源极区210和漏极区212通过用于形成半导体本体204的半导体材料电耦合在一起以形成源极连接垫(landing pad)310和漏极连接垫312，如图3A所示。或者，源极区210和漏极区212可以通过用于在功能电路中将各个晶体管200电互连到一起的较高层金属(例如，金属1、金属2、金属3)而耦合到一起。如图3A所示的晶体管200的栅极宽度等于通过每一个半导体本体204产生的栅极宽度的总和。通过这种方式，可以形成具有任意期望的栅极宽度的非平面或三栅极晶体管200。在本发明的实施例中，如上所述，每一个半导体本体204包括比顶部224细的底部222。
在本发明的实施例中，源极210和漏极212可以包括形成在在半导体本体204上并环绕该半导体本体的硅或其它半导体膜350，如图3B所示。例如，半导体膜350可以是硅膜或硅合金，例如硅锗(SixGey)。在本发明的实施例中，半导体膜350是所形成的具有与源极区210和漏极区212相同的导电类型的单晶硅膜。在本发明的实施例中，半导体膜可以是硅合金，例如硅锗，其中硅包括大约1-99原子百分比的合金。半导体膜350不必是单晶半导体膜，并且在实施例中可以是多晶膜。在本发明的实施例中，半导体膜350形成在半导体本体204的源极区210和漏极区212上以形成“升高”的源极和漏极区。半导体膜350可以通过一对诸如氮化硅或氧化硅或其组合物的介质侧壁隔离物360与栅电极电绝缘。如图3B所示，侧壁隔离物360沿着栅电极208的横向相对的侧壁260和262延伸，由此将半导体膜350与栅电极208绝缘。在本发明的实施例中，侧壁隔离物360具有介于20-200之间的厚度。通过增加半导体本体的源极和漏极区210和212的硅或半导体膜并形成“升高”的源极和漏极区，增加源极和漏极区的厚度，由此减小晶体管200的源极/漏极接触电阻以提高它的电特性和性能。
在本发明的实施例中，硅化物膜370，例如但不限于硅化钛、硅化镍、硅化钴，形成在源极区210和漏极区212上。在本发明的实施例中，硅化物370形成在半导体本体204上的硅薄膜350上，如图3B所示。然而，如果需要，硅化物膜370可以直接形成到硅本体204上。在自对准工艺(即自对准多晶硅化物工艺)中介质隔离物360使硅化物370能形成在半导体本体204或硅膜250上。
在本发明的实施例中，如果需要，当栅电极208是硅或硅锗膜时，硅膜350和/或硅化物膜370还可以形成在栅电极208的顶部。栅电极208上的硅膜350和硅化物膜370的形成减小了栅电极的接触电阻，由此改善了晶体管200的电性能。
图4A-4H示出形成具有变细的下本体部分的非平面晶体管的方法。晶体管的制造从衬底402开始。硅或半导体膜408形成在衬底402上，如图4A所示。在本发明的实施例中，衬底402是绝缘衬底，如图4A所示。在本发明的实施例中，绝缘衬底402包括下单晶硅衬底404和顶部绝缘层406，例如二氧化硅膜或氮化硅膜。绝缘层406将半导体膜408与衬底404绝缘，并且在实施例中形成为其厚度介于200-2000之间。绝缘层406有时被称为“掩埋氧化物”层。当硅或半导体膜408形成在绝缘衬底402上时，产生绝缘衬底上的硅或半导体(SOI)。
尽管半导体膜408在理想情况下为硅膜，但是在其它实施例中它也可以是其它类型的半导体膜，例如但不限于锗(Ge)、硅锗合金(SixGey)、砷化镓(GaAs)、InSb、GaP和GaSb。在本发明的实施例中，半导体膜408是本征(即未掺杂)硅膜。在其它实施例中，将半导体膜408掺杂为具有介于1×1016-1×1019原子/cm3之间的浓度水平的p型或n型导电性。可以对半导体膜408进行原位掺杂(即在沉积的同时进行掺杂)或在通过例如离子注入在衬底402上形成半导体膜408之后对其进行掺杂。在形成后进行掺杂使得能够容易地在相同的绝缘衬底上制造PMOS和NMOS三栅极器件。在这一点上半导体本体的掺杂水平可用于设置器件沟道区的掺杂水平。
半导体膜408形成为其厚度大约等于随后形成的半导体本体或制造的三栅极晶体管的本体所需要的高度。在本发明的实施例中，半导体膜408的厚度或高度409小于30纳米，并且在理想情况下小于20纳米。在本发明的实施例中，半导体膜408形成为其厚度大约等于希望制造的三栅极晶体管所具有的栅极“长度”。在本发明的实施例中，形成比希望器件所具有的栅极长度更厚的半导体膜408。在本发明的实施例中，形成半导体膜408使其厚度允许制造的三栅极晶体管对于其设计的栅极长度(Lg)能以全耗尽方式工作。
半导体膜408可以以任何公知的方法形成在绝缘衬底402上。在一种形成绝缘体上硅的衬底的方法(被称为SIMOX技术)中，以高剂量将氧原子注入到单晶硅衬底中，并且然后进行退火以形成衬底内的掩埋氧化物406。掩埋氧化物上方的单晶硅衬底的部分变为硅膜408。当前用于形成SOI衬底的另一技术是外延硅膜转移技术，其通常被称为结合的SOI。在该技术中，第一硅晶片具有生长在其表面上的薄氧化物，其稍后将用作SOI结构中的掩埋氧化物406。接着，将高剂量氢注入到第一硅晶片中以在第一晶片的硅表面之下形成高应力区域。然后，翻转该第一晶片并将其结合到第二硅晶片的表面上。然后沿着通过氢注入形成的高应力平面(stress plain)切割第一晶片。这导致顶部上具有薄硅层、下面的掩埋氧化物都处在单晶硅衬底的顶部上的SOI结构。可以使用公知的平滑技术，例如HCL平滑或化学机械抛光(CMP)，来将半导体膜408的顶表面平滑到所希望的厚度。
此时，如果需要，可以将绝缘区(未示出)形成到SOI衬底中以便使将要形成在其中的各个晶体管相互绝缘。可以通过利用例如公知的光刻和蚀刻技术蚀刻掉衬底膜408环绕三栅极晶体管的部分，并且然后利用诸如SiO2的绝缘膜回填所蚀刻的区域，来形成绝缘区。
在本发明的实施例中，硬掩模材料410形成在半导体膜408上，如图4A所示。硬掩模材料410是能为半导体膜408的蚀刻提供硬掩模的材料。硬掩模材料是能在半导体膜408的蚀刻期间保持其外形的材料。硬掩模材料410是在半导体膜408的蚀刻期间不蚀刻或仅轻微蚀刻的材料。在本发明的实施例中，硬掩模材料由这样的材料形成：其使得用于蚀刻半导体膜408的蚀刻剂蚀刻薄膜408至少比蚀刻硬掩模材料快五倍，并且在理想情况下至少快十倍。在本发明的实施例中，当半导体膜408是硅膜时，硬掩模材料410可以是氮化硅或氮氧化硅膜。形成硬掩模材料410使其厚度足以在半导体膜408的整个蚀刻期间保持其外形，但是又不能太厚以至于在对其的构图中产生困难。在本发明的实施例中，硬掩模材料410形成为其厚度介于3纳米到20纳米之间，并且在理想情况下小于10纳米。
接下来，还是如图4A所示，光刻胶掩模412形成在硬掩模层410上。光刻胶掩模412包含将要转移到半导体膜408中的特征图案。光刻胶掩模412可以通过任何公知的技术形成，例如通过覆盖沉积光刻胶材料，通过掩模，曝光和显影使光刻胶膜形成为具有用于将要被构图的半导体膜408的期望图案的光刻胶掩模412。光刻胶掩模412通常由有机化合物形成。形成光刻胶掩模412使其厚度足以在对硬掩模膜410进行构图的同时保持其外形，但是又不能太厚以至于阻止可能通过所使用的光刻系统和工艺而形成最小尺寸(即临界尺寸)的光刻构图。
接着，如图4B所示，与光刻胶掩模412对准蚀刻硬掩模材料410以形成如图4B所示的硬掩模414。光刻胶掩模412防止在下面的硬掩模材料410部分被蚀刻。在本发明的实施例中，利用能蚀刻硬掩模材料但不蚀刻下面的半导体膜208的蚀刻剂来蚀刻硬掩模。利用对下面的半导体膜208具有几乎完美选择性的蚀刻剂来蚀刻硬掩模材料。也就是，在本发明的实施例中，硬掩模蚀刻剂蚀刻硬掩模材料至少比蚀刻下面的半导体膜208快一百倍(即蚀刻剂具有至少50∶1的硬掩模对半导体膜的选择率)。当硬掩模材料414是氮化硅或氮氧化硅膜时，利用干法蚀刻工艺，例如反应离子蚀刻/电子回旋驻留等离子蚀刻，将硬掩模材料410蚀刻成硬掩模414。在本发明的实施例中，利用包括CHF3和O2和Ar/CH2F2和C4F8和Ar和O2的化学物质对氮化硅或氮氧化硅硬掩模进行反应离子蚀刻。
接着，如图4C所示，在将硬掩模膜410构图成硬掩模414之后，可以通过公知技术去除光刻胶掩模412。例如，可以利用包括硫酸和过氧化氢的“piranha”清洗溶液去除光刻胶掩模412。另外，利用O2灰化去除光刻胶掩模412的残余物。
尽管不需要，但希望在蚀刻半导体膜408之前去除光刻胶掩模412从而使来自光刻胶的聚合物膜不形成在图案化的半导体膜408的侧壁上。因为干法蚀刻工艺能腐蚀光刻胶掩模并导致聚合物膜逐渐形成在半导体本体的侧壁上，其很难被去除并且不利于器件性能，所以希望在蚀刻半导体膜408之前首先去除光刻胶掩模412。通过在对半导体薄膜408进行构图之前首先去除光刻胶膜412，可以对半导体薄膜408进行构图并保持原来的侧壁。
接着，如图4D所示，与硬掩模414对准蚀刻半导体膜408以形成具有一对横向相对的侧壁418和420的半导体本体416。硬掩模414防止在蚀刻工艺期间在下面的半导体膜208的部分被蚀刻。持续进行蚀刻直到到达下面的绝缘衬底。在本发明的实施例中，蚀刻“终点”在掩埋氧化物层406上。利用蚀刻半导体208而不显著蚀刻硬掩模414的蚀刻剂蚀刻半导体膜208。在本发明的实施例中，对半导体膜408进行各向异性蚀刻以使半导体本体416具有形成为与硬掩模414的侧壁对准的几乎垂直的侧壁418和420，由此提供与硬掩模414几乎完美的一致性(fidelity)。当硬掩414为氮化硅或氮氧化硅硬掩且半导体膜408为硅膜时，可以利用包括HBr/Ar/O2的干法蚀刻工艺来蚀刻硅膜408。
在本发明的实施例中，利用电子回旋驻留((electron cyclotronresidence)ECR)等离子蚀刻器蚀刻半导体本体408。在本发明的实施例中，使用包括压力在0.2到0.8帕斯卡之间的HBr/O2的化学物质和大约120瓦特的RF功率的ECR等离子蚀刻器用于将硅薄膜408蚀刻为硅本体416。这种蚀刻工艺产生基本上各向异性的蚀刻以提供基本上垂直的侧壁418和420，如图4D所示。另外，这种蚀刻具有对掩埋氧化物层406的高选择率(大约20∶1)以使掩埋氧化物层蚀刻得很少并且可以用作蚀刻停止和用于终点检测。终点检测的能力对于确保所有的半导体膜从掩埋氧化物层清除是很重要的，因为在整个晶片上的薄膜的厚度409可以变化且不同宽度的半导体本体的蚀刻速率也可以变化。在本发明的实施例中，使用在100-120瓦特之间的RF偏置。RF偏置控制蚀刻中的电子能量，其反过来控制蚀刻的各向异性分布。
接着，如图4F所示，蚀刻半导体本体416以减少在半导体本体416的下部分中的侧壁418和420之间的距离。使半导体本体的下部分变细的半导体本体的蚀刻可以被称为“外形”蚀刻。在本发明的实施例中，使用外形蚀刻以使侧壁418和420向内逐渐变细或形成侧壁418和420上的面422和424，如图4E所示。应该理解的是在本发明的其它实施例中，外形蚀刻可以使下本体部分变细，如图5A-5D所示。在本发明的实施例中，与半导体本体的上部分相比，使用产生各向同性蚀刻的等离子蚀刻工艺以减小半导体本体的下部分中的侧壁之间的距离。在本发明的实施例中，在外形蚀刻期间所使用的等离子蚀刻设备和蚀刻化学物质与在半导体膜408的构图期间所使用的等离子蚀刻设备和蚀刻化学物质相同，除了降低RF偏置以减小离子的垂直方向性。在本发明的实施例中，当半导体本体416是硅本体时，使用具有包括HBr/O2的化学物质和在0.2到0.8帕斯卡之间的压力且具有介于50-70瓦特之间的RF偏置的ECR等离子蚀刻器可以完成外形蚀刻。
接着，还如图4F所示，从具有变细的下本体部分的半导体本体416去除硬掩模414。在本发明的实施例中，当硬掩模414是氮化硅或氮氧化硅膜时，可以用包括磷酸和Di水的湿化学物质(wetchemistry)去除硬掩模。在本发明的实施例中，硬掩模蚀刻包括使用80-90％之间的磷酸(在体积上)和加热到150-170℃之间的温度且在理想情况下加热到160℃的Di水。这种蚀刻剂在氮化硅硬掩模214和掩埋氧化物层406之间将具有几乎完美的选择性。
接着，如果需要，在如图4F所示去除硬掩模414之后，可以将半导体本体416暴露给湿蚀刻剂以清洗本体416。在本发明的实施例中，硅本体416暴露给包括氢氧化氨(NH4OH)的液体蚀刻剂以去除任何的可能在硅本体416的构图期间形成的凹痕或线边缘粗糙。在本发明的实施例中，在30秒到2分钟之间的一段时间内在20-30摄氏度之间的温度下将硅本体416暴露给包括在体积上介于0.1-1％之间的氢氧化氨的蚀刻剂以便提供具有原始侧壁418和420的半导体本体416。
接着，如图4G所示，将栅介质层430形成在侧壁418和420以及半导体本体416的顶表面上。栅介质层可以是沉积的电介质或生长的电介质。在本发明的实施例中，栅介质层426是由干/湿氧化工艺生长的氮氧化硅介质膜。在本发明的实施例中，氧化硅膜生长成厚度介于5-15之间。在本发明的实施例中，栅介质层430是沉积的电介质，例如但不限于高介电常数膜，例如诸如五氧化钽(Ta2O5)、氧化钛(TiO2)、氧化铪、氧化锆和氧化铝的金属氧化物电介质。另外，在本发明的实施例中，栅介质层430可以是其它高k介质膜，例如但不限于PZT和BST。可以使用任何公知的技术沉积高k电介质，例如但不限于化学汽相沉积、原子层沉积和溅射。
接着，栅电极432形成在于半导体本体416的顶表面上形成的栅介质层430上并形成在栅介质层430上或邻近于栅介质层430，该栅介质层430形成在侧壁418和420上或邻近于侧壁418和420，如图4G所示。栅电极432具有与形成在绝缘层406上的底表面相对的顶表面且具有限定器件的栅极长度的一对横向相对的侧壁434和436。可以通过如下方式形成栅电极432：在衬底上覆盖沉积适当的栅电极材料，并且然后利用公知的光刻和蚀刻技术对栅电极材料进行构图以从栅电极材料形成栅电极432。在本发明的实施例中，栅电极材料包括多晶硅。在本发明的另一实施例中，栅电极材料包括多晶硅锗合金。在本发明的另一实施例中，栅电极材料可以包括金属膜，例如但不限于钨、钽和它们的氮化物。在本发明的实施例中，用于确定栅电极432的光刻工艺使用最少或最小尺寸的用于制造非平面晶体管的蚀刻工艺(也就是，在本发明的实施例中，栅电极432的栅极长度具有由光刻限定的晶体管的最小特征尺寸)。在本发明的实施例中，栅极长度小于或等于30纳米且在理想情况下小于20纳米。应该理解的是，尽管利用蚀刻掉不希望的部分的“消去”工艺形成如图4G和4H所示的栅介质层和栅电极，但是可以利用替换栅极工艺形成栅电极，在该工艺中首先形成牺牲栅电极，形成与其邻近的中间层电介质，然后去除牺牲栅电极以形成开口，然后在该开口中如本领域公知的那样形成栅电极。
接着，如图4H所示，然后在半导体本体416中、在栅电极432的相对侧上形成源极区440和漏极区442。对于PMOS晶体管，将半导体本体掺杂成浓度介于1×1020原子/cm3到1×1021原子/cm3之间的p型导电性。对于NMOS非平面晶体管，将半导体本体416掺杂成n型导电性，浓度介于1×1020原子/cm3到1×1021原子/cm3之间，以形成源极/漏极区。在本发明的实施例中，可以通过离子注入形成源极/漏极区。在本发明的实施例中，离子注入发生在垂直方向(即垂直衬底的方向)上，如图4H所示。栅电极432是多晶硅栅电极且可在离子注入工艺期间对其进行掺杂。栅电极432作为掩模以防止离子注入步骤掺杂非平面晶体管的沟道区。另外，沟道区是位于下面或由栅电极432环绕的半导体本体416的部分。如果栅电极432是金属电极，则在离子注入工艺期间可以使用介质硬掩模来阻挡掺杂。在其它实施例或其它方法中，例如可以使用固态源扩散来掺杂半导体本体以形成源极和漏极区。在本发明的实施例中，源极/漏极区还可以包括子区，例如源极/漏极延伸区和源极/漏极接触区。在这种情况下，将在栅电极432的任一侧上掺杂半导体本体416以形成源极/漏极延伸区，并且然后沿栅电极的侧壁形成如图3B所示的一对侧壁隔离物并使用第二掺杂步骤以形成如本领域公知的重掺杂源极/漏极接触区。另外，如果此时需要，可以将额外的硅和/或硅化物形成到半导体本体416上以形成升高的源极/漏极区并降低器件的接触电阻。这就完成了非平面器件的制造，该器件的半导体本体具有变细的下部分以改善器件性能。

Claims (25)

1、一种半导体器件，包括：
形成在衬底的绝缘层上的半导体本体，所述半导体本体具有与形成在所述绝缘层上的底表面相对的顶表面以及一对横向相对的侧壁，其中在所述顶表面处的所述横向相对的侧壁之间的距离大于在所述底表面处的所述横向相对的侧壁之间的距离；
形成在所述半导体本体的所述顶表面和所述半导体本体的所述侧壁上的栅介质层；
形成在所述半导体本体的所述顶表面和侧壁上的所述栅介质层上的栅电极；以及
形成在所述半导体本体中的、位于所述栅电极的相对侧上的一对源极/漏极区。
2、根据权利要求1所述的半导体器件，其中在所述半导体本体的所述底表面处的所述侧壁之间的所述距离大约是在所述半导体本体的顶表面上的所述侧壁之间的距离的1/2到2/3。
3、根据权利要求1所述的半导体器件，其中在大约所述半导体本体的中间部分处，所述半导体本体的所述侧壁之间的距离变得小于在顶表面处的所述半导体本体的所述侧壁之间的距离。
4、根据权利要求1所述的半导体器件，其中所述侧壁之间的距离在所述半导体本体的顶部是相同的，并且朝向所述半导体本体的底部而逐渐变小。
5、根据权利要求1所述的半导体器件，其中使得在所述半导体本体的底部处的所述侧壁之间的距离足够小以改善所述晶体管的短沟道效应。
6、根据权利要求1所述的半导体器件，其中在所述半导体本体的所述顶表面处的所述横向相对的侧壁之间的距离大约为30-20nm。
7、根据权利要求1所述的半导体器件，其中邻近在所述半导体本体的所述底部的所述横向相对的侧壁之间的距离大约为15-10nm。
8、一种半导体器件，包括：
形成在衬底的绝缘层上的半导体本体，所述半导体本体具有与形成在所述绝缘层上的底表面相对的顶表面以及一对横向相对的侧壁，其中所述横向相对的侧壁具有切面使得所述半导体本体的底部分比所述半导体本体的顶部更细；
形成在所述半导体本体的所述顶表面和所述半导体本体的所述侧壁上的栅介质层；
形成在所述半导体本体的所述侧壁和所述半导体本体的所述顶表面上的所述栅介质层上的栅电极；以及
形成在所述半导体本体中的、位于所述栅电极的相对侧上的一对源极/漏极区。
9、根据权利要求8所述的半导体器件，其中所述半导体本体包括硅。
10、根据权利要求8所述的半导体器件，其中邻近所述半导体本体的底表面的所述侧壁之间的距离大约是在所述半导体本体的顶部的所述侧壁之间的距离的50-66％。
11、一种形成器件的方法，包括：
在衬底的绝缘层上形成半导体本体，所述半导体本体具有与形成在所述绝缘层上的底表面相对的顶表面和一对横向相对的侧壁，其中在所述半导体本体的底表面处的所述横向相对的侧壁之间的距离小于在所述半导体本体的顶表面处的所述横向相对的侧壁之间的距离；
在所述半导体本体的所述顶表面和所述半导体本体的所述侧壁上形成栅介质层；
在所述半导体本体的所述顶表面上的所述栅介质层上形成栅电极，并且邻近于所述半导体本体的所述侧壁上的所述栅介质层形成所述栅电极；以及
在所述半导体本体中、在所述栅电极的相对侧上形成一对源极/漏极区。
12、根据权利要求11所述的方法，其中所述半导体本体的底部的宽度大约是所述半导体本体的顶部的宽度的1/2到2/3。
13、根据权利要求11所述的方法，其中所述侧壁之间的所述距离在所述半导体本体的顶部是相同的，而在所述半导体本体的底部附近逐渐减小。
14、根据权利要求11所述的方法，其中在顶表面处的所述半导体本体的所述侧壁之间的距离介于20-30nm之间，并且其中邻近底部的所述横向相对的侧壁之间的距离介于10-15nm之间。
15、一种形成晶体管的方法，包括：
提供具有形成在其上的氧化物绝缘层的衬底和形成在所述氧化物绝缘层上的半导体薄膜；
蚀刻所述半导体膜以形成具有与所述氧化物绝缘膜上的底表面相对的顶表面和一对横向相对的侧壁的半导体本体；
蚀刻所述半导体本体以相对于所述半导体本体的顶部减少邻近所述半导体本体的底部的横向相对的侧壁之间的距离；
在所述半导体本体的顶表面和侧壁上形成栅介质层；
在所述半导体本体的顶部上的所述栅介质层上形成栅电极并且邻近于所述半导体本体的侧壁上的所述栅介质层形成所述栅电极；以及
在所述半导体本体中、在所述栅电极的相对侧上形成一对源极/漏极区。
16、根据权利要求15所述的方法，其中所述半导体膜的所述蚀刻在所述氧化物绝缘层上停止。
17、根据权利要求15所述的方法，其中所述半导体本体包括硅，并且其中所述半导体膜的所述蚀刻是利用包括HBr/O2的化学物质的干法蚀刻工艺。
18、根据权利要求15所述的方法，其中所述半导体本体的所述蚀刻在不显著地蚀刻所述半导体本体的顶部的情况下减小邻近所述半导体本体的底部的横向相对的侧壁之间的距离。
19、根据权利要求18所述的方法，其中所述半导体本体是硅，并且通过利用包括HBr/O2的化学物质的干法蚀刻工艺对其进行蚀刻。
20、根据权利要求18所述的方法，其中在用于减少底部厚度的所述半导体本体的所述蚀刻期间所使用的功率使用介于50-70瓦特之间的RF偏置。
21、根据权利要求18所述的方法，其中用于减少所述半导体本体的底部上的侧壁之间的距离的蚀刻工艺使用介于150-180mL/min之间的总的HBr/O2气流。
22、根据权利要求15所述的方法，还包括在蚀刻所述半导体本体以减小邻近底部的所述半导体本体的横向相对的侧壁之间的距离之后，将所述半导体本体暴露给包括NHyOH的液体化学物质。
23、根据权利要求15所述的方法，其中用于形成所述本体的所述半导体膜的所述蚀刻使用第一工艺气体化学物质和第一RF偏置，并且用于减小所述底部的厚度的所述半导体本体的所述蚀刻使用第二工艺气体和第二RF偏置，其中所述第二RF偏置小于所述第一RF偏置。
24、根据权利要求23所述的方法，其中所述第一工艺气体与所述第二工艺气体相同。
25、根据权利要求24所述的方法，其中所述第一和第二工艺气体包括HBr/Ar/O2。
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US20160005829A1 (en) 2016-01-07

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