CN100555579C - Integrated circuit is made - Google Patents

Abstract

A kind ofly be used for defining first area (102) that method of patterning is included in substrate (108) and go up and use photoetching process in the first photoresist layer, to define a plurality of bodies at integrated circuit (100).Described method further comprises using and pitch-multipliedly produces at least two bodies (120) at each body in the described photoresist layer in bottom shielding layer (116).Described body in the described bottom masking layer (116) comprises annular termination (124).Described method further comprises the second area (104) that comprises annular termination (124) described in the described bottom masking layer (116) that covers described substrate (108) with the second photoresist layer (126).Described method further is included in passes the described body etched trench pattern in the masking layer of described bottom and does not etch in the described second area (104) in described substrate (108).Described groove has groove width.

Description

Integrated circuit is made

The priority application case

The application's case is advocated the rights and interests of the 60/666th, No. 031 U.S. Provisional Patent Application case (application on March 28th, 2005).The whole disclosure of described priority application case is incorporated herein by reference.

The reference of related application

The application's case and the 10/932nd, No. 993 U.S. patent application case (applications on September 1st, 2004, attorney docket MICRON.293A, Micron case 2003-1435.00/US), the 10/934th, No. 778 U.S. patent application case (applications on September 2nd, 2004, attorney docket MICRON.294A, Micron case 2003-1446.00/US), the 10/931st, No. 771 U.S. patent application case (applications on August 31st, 2004, attorney docket MICRON.295A, Micron case 2004-0068.00/US), the 10/934th, No. 317 U.S. patent application case (applications on September 2nd, 2004, attorney docket MICRON.296A, Micron case 2004-0114.00/US), the 11/215th, No. 982 U.S. patent application case (is applied for simultaneously with the application's case, attorney docket MICRON.313A, Micron case 2004-1065.00/US), the 60/662nd, No. 323 U.S. Provisional Patent Application case (applications on March 15th, 2005, attorney docket MICRON.316PR, Micron case 2004-1130.00/PR) and the 11/134th, No. 982 U.S. patent application case (applications on May 23rd, 2005, attorney docket MICRON.317A, Micron case 2004-0968.00/US) relevant.The whole contents of all these related application all is incorporated herein by reference.

Technical field

The present invention relates generally to the integrated circuit manufacturing, and more particularly relates to masking technique.

Background technology

Along with the increase in demand of portability, computing capability, memory span and energy efficiency in the hyundai electronics element, integrated circuit continues to make more and more forr a short time.Therefore, for example the size of the integrated circuit of electric installation and interconnection line width composition body also continues to reduce.In for example dynamic random access memory (" DRAM "), flash memory, nonvolatile memory, static RAM (" SRAM "), ferroelectric (" FE ") memory, logic gate array or the like memory circuitry or device, the trend that feature dimension reduces is tangible.

For instance, DRAM generally includes millions of the identical circuit elements that are called memory cell.In the most general form, memory cell is made up of two electric installations usually: holding capacitor and access field-effect-transistor.Each memory cell is can store a binary digit (" position ") but the addressable location of data.Can the position be written to the unit by transistor, and can read the position by the electric charge from reference electrode side sensing storage electrode.Form electric installation and it is carried out the size of the call wire of access by reducing, can reduce to incorporate into the size of the storage arrangement that these bodies are arranged.Therefore, by being coupled in the storage arrangement, more memory cell can increase memory capacity.

As another example, flash memory (for example, Electrically Erasable Read Only Memory or " EEPROM ") is for wipe and a class memory of programming again with block rather than a byte usually at every turn.Typical flash memory comprises the memory array that comprises a large amount of memory cells.Memory cell comprises the floating grid field-effect transistor that can keep electric charge.Data in the unit are by the existence of electric charge in the floating grid or do not have decision.The unit is grouped into the section that is called " erase blocks " usually.The memory cell of flash memory array is arranged to " NOR " structure (each unit is directly coupled to bit line) or " NAND " structure (unit is coupled to unit " string ", makes each unit be indirectly coupled to bit line and need to start other unit of going here and there to carry out access) usually.Can be by floating grid is charged with the unit in the random basis electricity program erase block.Electric charge accessible region piece erase operation removes from floating grid, wherein in single operation with all the floating gate memory cell erasure in the erase blocks.

The spacing of pattern is defined as the distance between the identical point in two adjacent patterns bodies.Usually define these bodies by the opening in the material of for example insulator or conductor, and make these body each intervals by described material.Therefore, the width at spacing width that can be regarded as body and the interval that described body is separated with adjacent body and.

Summary of the invention

In one embodiment of the invention, a kind of be used for defining at integrated circuit use photoetching process in the first photoresist layer, to define a plurality of bodies on the first area that method of patterning is included in substrate.Use and pitch-multipliedly in the shielding layer of bottom, produce at least two bodies at each body in the described photoresist layer.Body in the masking layer of described bottom comprises annular termination.The second photoresist layer covers the second area of the annular termination in comprising of described substrate of the described bottom masking layer.In described substrate, pass the described body etched trench pattern in the masking layer of described bottom under the situation in not etching into described second area.Described groove has groove width.

In another embodiment of the present invention, a kind of method of making a plurality of leads in array comprises provides membrane stack.Described membrane stack comprise the substrate that contacts with a plurality of conductive plungers, on overlay on dielectric film on the described conductive plunger, on overlay on lower mask layer on the described dielectric film, and be formed at the array of spacers on the described lower mask layer.Deposited sacrificial film on described lower mask layer and described array of spacers.On the part of described expendable film, form second mask.Described second mask defines the opening in the described array of spacers.Can be with respect to described second mask optionally described lower mask layer of etching and described sacrifice layer.The described expendable film of etching also exposes the part of described lower mask layer.Described method further comprises the described lower mask layer of etching and exposes the part of described dielectric film.The a plurality of grooves of etching are to expose at least a portion of described conductive plunger in described dielectric film, lower mask layer and expendable film.Carry out blanket metal deposition.In mosaic technology, be formed on the flat surfaces that replaces between described metal and the dielectric film.

In another embodiment of the present invention, a kind of pitch-multiplied method that is used for the integrated circuit damascene features comprises provides substrate.Carry out first masking process on described substrate, to define the array of spacer lines.Described spacer lines is separated by a plurality of gaps.Carry out second masking process with the part of the described spacer lines of locking and in the logic region of described integrated circuit, define a plurality of cross tie parts.The a plurality of grooves of etching in the gap between described spacer lines.Depositing metal layers is to form a plurality of metal wires in the gap between spacer lines.Described integrated circuit possesses the surface of flat in mosaic technology.

In another embodiment of the present invention, a kind of method that forms integrated circuit package on substrate comprises to be used lithography technique patterning first resist layer and defines a plurality of lines.Use pitch multiplication techniques to form spacer pattern on every side in the zone of defining by described a plurality of lines.Described distance piece comprises the ring with the terminal elongation of ring.Deposition second resist layer is to define the blocked region of described substrate on described ring end.Described method further is included under the situation about not etching in the described blocked region, and optionally etching is passed described distance piece to form a plurality of grooves in described substrate.

Description of drawings

In the accompanying drawing explanation integrated circuit that only is used for illustration purpose and the one exemplary embodiment of ic manufacturing technology.Accompanying drawing comprises following each figure, and it is not necessarily drawn in proportion.Same numeral is represented same parts among each figure.

Figure 1A is formed with the cross-sectional view of the substrate of a plurality of mask lines above being.

Figure 1B is the cross-sectional view of the substrate of Figure 1A after the anisotropic etching process of mask pattern being transferred in the temporary layer.

Fig. 1 C is the cross-sectional view of the substrate of Figure 1B after removing mask lines and carrying out isotropism " contraction " etching.

Fig. 1 D is the cross-sectional view of the substrate of Fig. 1 C after the spacer materia that is retained in the axle in the temporary layer being carried out blanket-deposited.

Fig. 1 E is the cross-sectional view of the substrate of Fig. 1 D after being used to stay the directed spacer etch technology of pitch-multiplied body or distance piece.

Fig. 1 F is the cross-sectional view of the substrate of Fig. 1 E after removing axle.

Fig. 2 is the top schematic view of the integrated circuit of exemplary part formation.

Fig. 3 forms a plurality of pitch-multiplied bodies schematic, cross-sectional side view of the integrated circuit of the part formation of Fig. 2 afterwards in substrate with on the substrate.

Fig. 4 is that the integrated circuit that the part of Fig. 3 forms is formed with dielectric film schematic, cross-sectional side view afterwards thereon.

Fig. 5 is that the integrated circuit that the part of Fig. 4 forms is formed with hard mask layer schematic, cross-sectional side view afterwards thereon.

Fig. 6 A is that the integrated circuit that the part of Fig. 5 forms is formed with a plurality of distance pieces schematic, cross-sectional side view afterwards thereon.

Fig. 6 B is the top schematic view of the integrated circuit that forms of the part of Fig. 6 A.

Fig. 7 is that the integrated circuit that the part of Fig. 6 A forms deposits bottom antireflective coating (" BARC ") schematic, cross-sectional side view afterwards thereon.

Fig. 8 A is that the integrated circuit that the part of Fig. 7 forms is formed with second photoresist pattern schematic, cross-sectional side view afterwards thereon.

Fig. 8 B is the top schematic view of the integrated circuit that forms of the part of Fig. 8 A.

Fig. 9 is the schematic, cross-sectional side view of the integrated circuit that forms of the part of Fig. 8 A after the etching bottom antireflective coating.

Figure 10 A is the schematic views of the integrated circuit that forms of the part of Fig. 9 after passing the distance piece and the second photoresist pattern etching hard mask layer; Described view is the cross section that intercepts along the line perpendicular to spacer loop.

Figure 10 B is the schematic views of the integrated circuit that forms of the part of Fig. 9 after passing the distance piece and the second photoresist pattern etching hard mask layer; Described view is the cross section along the length intercepting of spacer loop.

Figure 11 is at the etching dielectric film and the schematic cross section of the integrated circuit that the part of Figure 10 A forms after removing photoresist, BARC and distance piece.

Figure 12 is that the integrated circuit that the part of Figure 11 forms deposits electric conducting material schematic cross section afterwards thereon.

Figure 13 is the schematic cross section of integrated circuit of the part formation of Figure 12 after carrying out chemical mechanical planarization process.

Figure 14 is the flow chart that the exemplary processes of some structure in the integrated circuit structure that is used to form this paper announcement is described.

Figure 15 is the top schematic view that comprises the integrated circuit that the part of spacer loop and metal level forms.

Figure 16 is the schematic cross section of the integrated circuit that forms of the part of Figure 13, and it further is included in the mistake top contact part between array region and the outer peripheral areas.

Figure 17 A is the layout by first mask of photoetching process formation; Described first mask defines a plurality of axles.

Figure 17 B is by the axle of Figure 17 A being carried out the layout of the spacer pattern that pitch multiplication techniques obtains.

Figure 17 C is the layout that applies the integrated circuit that part that second metal mask forms forms by the spacer pattern to Figure 17 B.

Embodiment

The technology that continues to reduce being used to form body of feature dimension proposes increasing demand.For instance, photoetching process is generally used for the body on the substrate (for example, line) is carried out patterning.The notion of spacing can be used for describing the size of these bodies.Yet because the cause of the optical considerations of light or radiation wavelength for example, lithography technology has minimum spacing, can't form body reliably under described minimum spacing.Therefore, the minimum spacing of photoetching technique can limit feature dimension and reduces.

Doubling range interval is to extend beyond a kind of method that its minimum spacing proposes for the ability that makes photoetching technique.The method illustrates in Figure 1A-1F and the 5th, 328, describes in No. 810 United States Patent (USP)s (on July 12nd, 1994 issued) that the whole disclosure of described United States Patent (USP) is incorporated herein by reference.Referring to Figure 1A, at first use photoetching process in the photoresist layer that overlies interim or expendable material layer 20 and substrate 30, to form line pattern 10.Be used to carry out photolithographic common wavelengths including (but not limited to) 157nm, 193nm, 248nm or 365nm.Shown in Figure 1B, then design transfer is arrived temporary layer 20 by etching step (for example, the anisotropic etching step), form occupy-place thing (placeholder) or axle 40 whereby.Photoresist line 10 can peel off and axle 40 can be through isotropic etching to increase the distance between the adjacent axle 40, shown in Fig. 1 C.Deposition of spacer material layer 50 on axle 40 subsequently is shown in Fig. 1 D.Then by in directed spacer etch from the horizontal plane spacer etch material and form distance piece 60 preferentially in the sidepiece of axle 40, shown in Fig. 1 E.Then remove all the other axles 40, only stay the distance piece 60 that serves as the mask that is used for patterning jointly, shown in Fig. 1 F.Therefore, before once defined at given area of the pattern under the situation at a body and an interval (respectively have width F, thereby obtain spacing 2F), identical area of the pattern now comprises two bodies and two intervals, define (respectively have width 1/2F, thereby obtain spacing F) as distance piece 60.Therefore, by using the doubling range interval technology to reduce photoetching technique minimum feature size in the cards effectively.

Although in fact spacing is halved in above example, this spacing reduces conventionally to be called spacing and " doubles " or more generally be called spacing " multiplication ".That is to say that in fact the spacing " multiplication " that conventionally multiply by a certain multiple relates to makes spacing reduce described multiple.This paper has kept conventional term.It should be noted that by on distance piece, forming distance piece, can further reduce the feature dimension that can define.Therefore, pitch-multipliedly be meant described process substantially, and no matter the number of times that the distance piece forming process is used how.

Because layer of spacer material 50 has single thickness 90 (seeing Fig. 1 D and 1E) usually, and because the size of the body that forms by distance piece 60 usually corresponding to described thickness 90, so the common generation of doubling range interval technology only has a kind of body of width.Yet integrated circuit often comprises the body with different size.For instance, RAM circuit contains memory cell array and logical circuit usually in so-called " periphery ".In array, memory cell is connected by lead usually, and in the periphery, lead contacts bumping pad usually to be used for that array is connected to logic.Yet for example the peripheral features of bumping pad may be greater than lead.In addition, for example transistorized peripheral electrical devices is preferably more than the electric installation in the array.And, even peripheral features can be formed with the spacing identical with array, under the situation of using single mask, also can not realize defining the required flexibility of circuit usually, especially when pattern is limited to those patterns that can form along the sidewall of resist pattern.

Being used for of some propositions peripheral and form method of patterning at the array place and relate to three independent masks.For instance, in a method, first mask and doubling range interval are used to form spacer pattern, and it is usually included in the spacer loop in the zone (for example, the array region of storage arrangement) of chip.Then, carry out second mask and in another zone of chip (for example, the outer peripheral areas of storage arrangement), form second pattern.This second peripheral pattern is formed in the layer that overlays on the spacer pattern.It covers the middle body of spacer loop, and the annular termination of distance piece stays to stand etch process.Then, carry out that the 3rd mask is included in the outer peripheral areas with formation and/or from the 3rd pattern of the cross tie part of outer peripheral areas.Then " chopping " spacer pattern and the 3rd pattern are transferred to the shielding layer that underlies, can be with respect to the described shielding layer of the substrate etch that underlies.This allows to have different size, and the body of (compare each other and compare with spacer loop) is formed in the circuit peripheral region.This type of body is including (for example) interconnect patterns.These bodies can be overlapping with spacer loop, can merge with body in the gate array zone, and can be with after etching.

According to foregoing, developed improved technology and be used to form body, especially for having the pitch-multiplied body of overlapping pattern with different size.

In certain embodiments, the part that will transfer to substrate of feature pattern has the spacing of the minimum spacing that is lower than the photoetching technique that is used to handle substrate.In addition, some embodiment can be used for forming the device with array of electrical devices, comprises logic sum gate array and volatibility and non-volatile memory device, for example DRAM, read-only memory (" ROM "), flash memory and gate array.In this type of device, form (for example) transistor gate and lead in the pitch-multiplied array region that is used in chip, and conventional photoetching process is used in the periphery of chip and forms for example big body of contact.Exemplary in making the process of storage arrangement covered that step illustrates in the drawings and described in this article.

Fig. 2 shows the top view of the integrated circuit 100 (for example, memory chip) that exemplary part is made.Central array region 102 is centered on by outer peripheral areas 104.To understand, after making integrated circuit 100, array 102 will be equiped with lead and electric installation, for example transistor and capacitor usually thick and fast.Pitch-multiplied being used in the array region 102 forms body, as discussed herein.On the other hand, outer peripheral areas 104 optionally comprises the body greater than the body in the array region 102.Conventional photoetching process (being not pitch-multiplied) is generally used for these big bodies of patterning, and the example of described body comprises various types of logical circuits.The geometric complexity that is arranged in the logical circuit of outer peripheral areas 104 make be difficult to use pitch-multiplied.By contrast, the regular grids as typical array pattern is of value to pitch-multiplied.In addition, some devices in the outer peripheral areas 104 may be owing to electrical limitations needs bigger physical dimension, makes that whereby pitch-multiplied for this type of installs to be not so good as conventional photoetching process favourable.Except the possible difference of relative scale, in other embodiments, the outer peripheral areas 104 in the integrated circuit 100 and the relative position of array region 102 and number also can change.

The partial cross section view of the integrated circuit that the part of Fig. 3 exploded view 2 is made, it comprises the several portions of array region 102 and outer peripheral areas 104.Use lithography technology, a plurality of grooves of etching in substrate 108, and these trench fill have insulator 105, for example oxide.Insulator 105 is a field isolating layer, and in an exemplary embodiment at high-density plasma (" HDP "), spin-on dielectric (" SOD "), flow fill or TEOS technology in the shallow trench isolation that deposits from (" STI ") layer.In an exemplary embodiment, SOD is deposited and denseization.

On substrate, form upper interlevel dielectric (" ILD ") insulator 106, and make the contact that passes ILD 106 by the etching contact hole and with conductive plunger 110 fillings.In one embodiment, conductive plunger 110 comprises polysilicon, but can use other electric conducting material in other embodiments.The several portions of etching stopping layer 112 (for example, nitride layer) is set on insulator 106; Etching stopping layer 112 is used to form conductive plunger 110.In certain embodiments, insulator 105 is aimed at substrate/plug interface.Yet in other embodiments, insulator 105 extends and is slightly higher than substrate/plug interface, and is illustrated as Fig. 3.

In the illustrated one exemplary embodiment of Fig. 3, the feature dimension in the array region 102 is less than the feature dimension in the outer peripheral areas 104.In one embodiment, conductive plunger 110 has the feature dimension of about 50nm.In a preferred embodiment, conductive plunger 110 has the feature dimension between about 30nm and about 100nm.More preferably, conductive plunger has the feature dimension between about 32.5nm and about 65nm.Can use other feature dimension of conductive plunger 110 in other embodiments.Additional detail about the technology that is used to form conductive plunger is provided in the 11/215th, No. 982 U.S. patent application case (applying for attorney docket MICRON.313A, Micron case 2004-1065.00/US with the application's case simultaneously).

Illustrated as Fig. 4, the insulator film 114 that wherein will form mosaic groove is deposited on the membrane stack illustrated in fig. 3.In one embodiment, insulator film comprises unadulterated oxidation film, and for example by the oxidation film of tetraethyl orthosilicate salt (" TEOS ") deposition, and in other embodiments, insulator film comprises the oxidation film of doping, for example BPSG or PSG.Can use other non-oxide insulators in other embodiments.In an exemplary embodiment, insulator film 114 deposits to corresponding to the thickness that will be formed at the conductor height in the integrated circuit.

Illustrated as Fig. 5, hard mask layer 116 is deposited on the insulator film 114.In one embodiment, hard mask layer 116 comprises amorphous silicon, but can use other material in other embodiments.

Illustrated as Fig. 6 A, a plurality of distance pieces 118 are formed on the hard mask layer 116.In an exemplary embodiment, use the doubling range interval technology of the technology that Figure 1A for example illustrates in the 1F, use the photoresist mask, transfer, isotropic etching and the spacer process that are disclosed to form distance piece to temporary layer.In an exemplary embodiment, comprise can be with respect to the optionally etched low temperature oxide material of the hard mask layer 116 that underlies for distance piece.For instance, in one embodiment, with less than about 400 ℃ temperature deposition of spacer.In another embodiment, use the atom layer deposition process deposition of spacer.The exemplary materials that is used for distance piece comprises silica, silicon nitride, polysilicon and carbon.

Between distance piece 118 is gap 120, and it is corresponding to the zone that will deposit electric conducting material of integrated circuit.In the illustrated one exemplary embodiment of Fig. 6 A, gap 120 and conductive plunger 110 perpendicular alignmnets.

In an exemplary embodiment, the interval between distance piece 118 and the gap 120 changes between the array region 102 of integrated circuit 100 and outer peripheral areas 104.This further specifies in Fig. 6 B, the top view in Fig. 6 B signal showroom spacing body 118 and intervention gap 120.Fig. 6 B illustrates that also distance piece 118 follows the profile that is formed at the line in the layer that light can define substantially, forms a plurality of annular terminations 124 whereby.

Illustrated as Fig. 7, BARC 122 is coated on the distance piece 118.In spin coating proceeding, apply BARC 122, the surface of flat is provided whereby.After BARC 122 is coated on the distance piece 118, apply second mask.Second mask causes the pattern of photoresist 126 to be deposited on the integrated circuit.Photoresist pattern defining blocked region, the annular termination 124 of its locking distance piece 118 also defines one or more openings 128 in outer peripheral areas 104.This explanation in Fig. 8 A (end view) and 8B (top view).Illustrated as Fig. 8 B, in an exemplary embodiment, second mask and distance piece 118 spaced apart gap 120a, and with the terminal 124 spaced apart gap 120b of distance piece ring-type.Gap 120a, 120b adapt to the misalignment of second mask with respect to spacer pattern.

In an exemplary embodiment, the minimum widith of opening 128 depends on the resolution of photoetching process own, and described resolution is low to moderate 100nm in one embodiment, is low to moderate 65nm in another embodiment, and is low to moderate 45nm in another embodiment.Can use other size in other embodiments.In an exemplary embodiment, the distance piece in the gate array zone 104 118 is fully spaced apart to allow contact 132 " landing " so that the interconnection of other layer that arrives integrated circuit to be provided.

In an exemplary embodiment, after carrying out second mask, etching BARC 122, illustrated as Fig. 9.In modified embodiment, the pattern that is defined by second mask that comprises blocked region was transferred to the intermediate layer before etching BARC.In this type of embodiment, intermediate layer or independent BARC are used for the annular termination 124 of locking distance piece 118.

Is the etching of hard mask layer 116 after the BARC etching, can be with respect to distance piece 118 etch hard mask layer 116 optionally.The structure of gained is in Figure 10 A (along the cross-sectional view perpendicular to the intercepting of the line of spacer loop) and explanation in Figure 10 B (along the cross-sectional view of the length intercepting of spacer loop).In one embodiment, hard mask etching is a dry etch process.After this is to remove photoresist 126 and BARC 122 continuously, is oxide etching afterwards.In this type of embodiment, oxide etching will remove the expose portion of distance piece 118 and insulator film 114.Conductive plunger 110 provides etching to stop.Resulting structures illustrated in fig. 11 comprises the pattern of the groove that the conductive plunger that makes in the array region 102 110 exposes and the pattern of other opening 128 in the hard mask layer 116 in the outer peripheral areas 104.This operation has advantageously reduced effective aspect ratio of groove.In modified embodiment, the insulator film 114 that under the situation that had not before removed distance piece 118, illustrates among etch figures(s) 10A and the 10B.At backing material is optionally to omit BARC 122 among non-reflexive embodiment.

No matter how groove to form, the etch process of explanation advantageously merges two mask patterns among Figure 10 A, the 10B and 11: the pattern that is formed by the distance piece in the array region 102 118, and the pattern that is formed by the photoresist in the outer peripheral areas 126.This forms effectively has the overlapping of two distinct patterns, and it allows etching to pass gap 120 between the distance piece 118 in the zone that is not covered by the second photoresist layer 126 of integrated circuit 100.

Illustrated as Figure 12, in an exemplary embodiment, electric conducting material 130 then is deposited on the integrated circuit of part formation.Optionally, before deposits conductive material 130, remove hard mask layer 116.Suitable electric conducting material is including (but not limited to) titanium, titanium nitride, tungsten, tantalum nitride and copper.In an exemplary embodiment, electric conducting material 130 deposits to the thickness that is enough to make that the wideest groove width is filled in the periphery.After deposits conductive material, use chemical-mechanical planarization (" CMP ") technology to separate the conductor in the groove and provide flat surfaces as integrated circuit.The structure of gained illustrates in Figure 13.

The flow chart of the exemplary processes that is used to form some structure in the integrated circuit structure that this paper discloses of furnishing an explanation among Figure 14.As described, in operational block 150, define a plurality of bodies in first resist layer in the array region of storage arrangement.The example that can be used for defining the resist layer of body is photoresist layer and mint-mark resist layer.Based on these bodies, in operational block 152, in the shielding layer of bottom, use pitch-multiplied a plurality of spacer loop that define.In modified embodiment, spacer loop is formed on the patterned resist body, but this is more not preferred, because resist can not bear spacer deposition and etch process usually.In operational block 156, use the end of the second resist layer locking spacer loop of the body in the outer peripheral areas that also defines integrated circuit.After applying second resist layer, the insulating barrier in the gap in operational block 158 between the spacer etch is carried out described etching with the pattern that is defined by second resist layer.Then can in operational block 160, on the integrated circuit that part forms, carry out metal filled and subsequent CMP technology, allow in the integrated circuit (IC) array zone, to form metal wire (operational block 162) whereby and in the integrated circuit outer peripheral areas, form electrical interconnection (operational block 164).Cross tie part optionally is used to connect peripheral interior integrated circuit package, for example logic module.Perhaps, second mask can define other pattern (for example, capacitor, contact, resistor), the spacer loop of locking simultaneously.

In certain embodiments, peripheral cross tie part also optionally is used to form being electrically connected between array region 102 and the outer peripheral areas 104.This explanation in the operational block 166 of Figure 14.For instance, this type of contact can be formed in the plane that is higher than mosaic texture illustrated in fig. 13.Provide this type of " to cross and push up " example of contact among Figure 16.As described, cross the top contact part and comprise a plurality of contacts 146 that connect by interconnection line 148.

Figure 17 A provides the top-down view of the one exemplary embodiment of method illustrated in fig. 14 to 17C.In particular, Figure 17 A illustrates first mask 134 that is defined by photoetching process.In one embodiment, first mask 134 is defined in the photo anti-corrosion agent material layer, but in other embodiments, first mask 134 is transferred to another layer, for example amorphous carbon layer.Figure 17 B explanation is at first shunk first mask 134 by using isotropic etching, and then carries out the doubling range interval technology produce spacer pattern 136 on first mask that shrinks.Apply second metal mask 138 and produce the demonstrative structure that illustrates among Figure 17 C.This structure comprises the widened section in the spacer pattern, and it is configured to hold the contact 139 from other layer of integrated circuit.

Some technology in the ic manufacturing technology that this paper discloses provides the remarkable advantage that is better than routine techniques.For instance, conventional method needs three independent masks to define array region, defines outer peripheral areas and removes the annular termination of circuit features.By contrast, some technology in the technology of this paper announcement allows to form body that spacing reduces in the mosaic technology of only using two masks.As described herein, in an exemplary embodiment, the available same mask that is used to define peripheral features is come the annular termination of locking array body.

Some embodiment on the other hand in, provide rule so that circuit designers is implemented the method for manufacturing integrated circuit that this paper discloses.The configuration of mask is indirectly corresponding to formed integrated circuit patterns, when especially the circuit features of being paid close attention to is defined in the gap between spacer loop (some of them are closed and some are not closed).Can disclose as this paper uses pitch-multiplied and embedding technique forms this type of body.Hereinafter the rule of Lun Shuing is provided for building to circuit designers and puts the guidance that can use the circuit that technology that this paper discloses forms.As described herein, build circuits and defer to these rules, allow to mix and use cross tie part, only use two masks simultaneously with various spacing dimensions.Specifically, spacer layers mask or " distance piece " are used for defining the distance piece that the spacing between the intensive interconnection line in gate array zone reduces, and metal level mask or " metal " are used for defining the interconnection pattern of circuit peripheral region.

In an exemplary embodiment, be used to define the design rule of distance piece and metal based on two proportionality factors.For given lithography, F is analysable minimum feature size, and D is the maximum misalignment that allows between two masks.Variable x is the pitch-multiplied proportionality constant (0＜x＜1) corresponding to the feature dimension of the spacer loop that is used to define metal wire.Because use single pitch multiplication techniques, so the attainable actual interconnect pitch of technology of using this paper to disclose is F.

In one embodiment, in a plurality of different closed hoop of not overlapping or intersection, extract spacer loop.Two exemplary spacer loops 140 of explanation among Figure 15, Figure 15 is the exemplary top view of simplifying for explanation that is in the integrated circuit in the manufacture process.As described, spacer loop has minimum widith xF, and has minimum interval (1-x) F.

In this type of embodiment, a plurality of metal feature 144 are defined by a plurality of spacer loop 140.Because use mosaic technology in a preferred embodiment, so metal feature 144 is defined in the gap between the spacer loop (some of them are closed and some are not closed), described metal feature 144 will deposit (for example, by physical vapour deposition (PVD) or chemical vapour deposition (CVD)) subsequently or use plated with conductive material.In addition, metal feature 142 is only defined by spacer loop 140 in a side.The metal feature 144 that is defined by spacer loop 140 in both sides has minimum widith (1-x) F.Only the metal feature 142 that is defined by spacer loop 140 in a side has minimum widith ((1-x) F+D).Metal feature also can form the minimum widith F that has corresponding to the minimum resolution of lithography technique under the situation of the restriction that does not have spacer loop 140.Illustrated as Figure 15, metal feature 144 has minimum interval xF when being separated by spacer loop 140, and metal feature 142 only a side by the space every or have minimum interval F when separating by spacer loop 140.If metal feature 142 or 144 is present in the both sides of spacer loop 140, contacts with spacer loop 140 so and extract metal (that is, metal occupies the occupation of land space directly contiguous with spacer loop 140).If metal feature 142 exists only in a side of spacer loop 140, minimum interval min (D-xF, 0) makes metal feature 144 separate with spacer loop 140 so.

The ic manufacturing technology that the circuit design rule that this paper describes in detail discloses based on this paper.In particular, use especially big spacer mask to define the interval that body that spacing subsequently reduces has limited the metal wire that the body that reduced by spacing defines.

The rule that provides according to the one exemplary embodiment that is disclosed by this paper defines metal separately and spacer layers allows circuit designers to come building integrated circuits based on the side circuit body that will appear on the wafer.These rules have advantageously solved the inherent limitations that occurs when using pitch multiplication techniques to form circuit features.The use of scale parameter x allows these design rules to work with the following pitch multiplication techniques that can produce less feature dimension.

Some embodiment that this paper discloses can be used for forming various integrated circuits.The example of this adhesive integrated circuit is including (but not limited to) (for example for example having volatibility and non-volatile memory device, DRAM, ROM or flash memory, NAND flash memory) memory cell array array of electrical devices circuit and have the integrated circuit of logic sum gate array.For instance, logic array can be field programmable gate array (" FPGA "), the ancillary equipment that it has the core array of the memory array of being similar to and has the logical circuit of support.Therefore, the integrated circuit that the technology of using this paper to disclose forms can be memory chip or the processor that (for example) can comprise logic array and in-line memory, perhaps has other integrated circuit of logic sum gate array.

Scope of the present invention

Although above-mentioned embodiment discloses some embodiment of the present invention, should be appreciated that this disclosure only is illustrative and does not limit the present invention.Should be appreciated that customized configuration that is disclosed and operation can be different from above-described those configurations and operation, and can use method described herein in the situation except that the integrated circuit manufacturing.

Claims (30)

1. method of in array, making a plurality of leads, described method comprises:

Membrane stack is provided, described membrane stack comprise the substrate that contacts with a plurality of conductive plungers, on overlay on dielectric film on the described conductive plunger, on overlay on the lower mask layer on the described dielectric film and be formed at array of spacers on the described lower mask layer;

Deposited sacrificial film on described lower mask layer and described array of spacers;

Form Etching mask on the part of described expendable film, described Etching mask defines the opening on the described array of spacers, wherein can be with respect to described Etching mask optionally described lower mask layer of etching and described expendable film;

The described expendable film of etching also exposes the part of described lower mask layer;

The described lower mask layer of etching also exposes the part of described dielectric film;

The a plurality of grooves of etching are to expose at least a portion of described conductive plunger in the expose portion of described dielectric film;

Execution enters the metal deposition in described a plurality of groove; And

In mosaic technology, be formed on the flat surfaces that replaces between described metal and the described dielectric film.

2. method according to claim 1, wherein said Etching mask further define a plurality of cross tie parts of the outer peripheral areas that is connected to described array outside.

3. method according to claim 1, wherein said substrate is an insulator.

4. method according to claim 1 wherein provides described membrane stack to comprise and uses photoetching process to form described array of spacers.

5. method according to claim 1, wherein said groove formed top bit line array.

6. method according to claim 1, it removes described array of spacers before further being included in the described a plurality of grooves of etching.

7. method according to claim 1, it removes described array of spacers, described Etching mask and described expendable film before further being included in the described a plurality of grooves of etching.

8. method according to claim 1, wherein said array of spacers has a plurality of annular terminations, and wherein said Etching mask covers the annular termination of described array of spacers.

9. method according to claim 1, wherein said array are memory array.

10. method according to claim 1, wherein said array are logic array.

11. method according to claim 1, wherein said array forms the part of flash memory device.

12. method according to claim 1, wherein said expendable film are dielectric film.

13. method according to claim 1, wherein said expendable film are bottom antireflective coating.

14. method according to claim 1, wherein said distance piece is selected from the group that is made up of silica, silicon nitride, polysilicon and carbon.

15. method according to claim 1 wherein uses atom layer deposition process to deposit described distance piece.

16. method according to claim 1 wherein deposits described distance piece with the temperature less than 400 ℃.

17. method according to claim 1, wherein said distance piece has the feature dimension between 30nm and 100nm.

18. method according to claim 1, wherein said distance piece has the feature dimension between 32.5nm and 65nm.

19. method according to claim 1, wherein said distance piece has the feature dimension of the feature dimension that equals described conductive plunger.

20. method according to claim 1, wherein said expendable film form smooth surface on described array of spacers.

21. the storage arrangement that part forms, it comprises:

Be arranged in a plurality of distance piece definition wires of the array region of described storage arrangement, wherein said distance piece definition wires forms the closed hoop end; And

On overlay on resist layer on the part of comprising of described distance piece definition wires of described closed hoop end, wherein said resist layer extends in the outer peripheral areas of described storage arrangement, and further defines a plurality of bodies in described outer peripheral areas.

22. the storage arrangement that part according to claim 21 forms overlays on the substrate on the wherein said distance piece definition wires.

23. the storage arrangement that part according to claim 21 forms, wherein said distance piece definition wires comprises silicon.

24. the storage arrangement that part according to claim 21 forms, wherein said distance piece definition wires comprises silica or nitride spacer.

25. the storage arrangement that part according to claim 21 forms overlays on the substrate that comprises wire array on the wherein said distance piece definition wires.

26. the storage arrangement that part according to claim 21 forms, wherein said distance piece definition wires has the feature dimension between 30nm and 100nm.

27. the storage arrangement that part according to claim 21 forms, wherein said distance piece definition wires has the feature dimension between 32.5nm and 65nm.

28. the storage arrangement that part according to claim 21 forms, wherein said distance piece definition wires has the feature dimension between 22nm and 45nm.

29. the storage arrangement that part according to claim 21 forms, wherein said resist layer comprises photoresist.

30. the storage arrangement that part according to claim 21 forms, wherein said distance piece definition wires is through pitch-multiplied spacer lines.

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