CN100530563C - Process capable of improving film uniformity before chemical mechanical grinding - Google Patents

Process capable of improving film uniformity before chemical mechanical grinding Download PDF

Info

Publication number
CN100530563C
CN100530563C CNB2005100294010A CN200510029401A CN100530563C CN 100530563 C CN100530563 C CN 100530563C CN B2005100294010 A CNB2005100294010 A CN B2005100294010A CN 200510029401 A CN200510029401 A CN 200510029401A CN 100530563 C CN100530563 C CN 100530563C
Authority
CN
China
Prior art keywords
sih
flow
frequency power
mechanical grinding
chemical mechanical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2005100294010A
Other languages
Chinese (zh)
Other versions
CN1925117A (en
Inventor
胡正军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai IC R&D Center Co Ltd
Shanghai Huahong Group Co Ltd
Original Assignee
Shanghai Huahong Group Co Ltd
Shanghai Integrated Circuit Research and Development Center Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huahong Group Co Ltd, Shanghai Integrated Circuit Research and Development Center Co Ltd filed Critical Shanghai Huahong Group Co Ltd
Priority to CNB2005100294010A priority Critical patent/CN100530563C/en
Publication of CN1925117A publication Critical patent/CN1925117A/en
Application granted granted Critical
Publication of CN100530563C publication Critical patent/CN100530563C/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

This invention relates to one process to improve CMP front film in the semiconductor integration circuit, which adjusts HDP CVD depositions parameters and overlaps the HDP CVD and TEOS PECVD film to effectively improve CMP film even property.

Description

A kind of process of improving film uniformity before chemical mechanical grinding
Technical field
The invention belongs to the semiconductor integrated circuit manufacturing process technology field, a kind of technology of improving the preceding uniformity of film of CMP (cmp).
Background technology
In traditional Al (aluminium) interconnection technique, metal A l carries out medium and fills after etching.At different process nodes different implementation methods is arranged.In early days, for metal wire separation>0.5um, depth-width ratio<0.8, relatively typical method is deposit/sputter/deposit.At first be to be presoma with PECVD (plasma auxiliary chemical vapor deposition) SiO with TEOS (tetraethyl orthosilicate) 2(silicon dioxide) is that the sputter of Ar (argon gas) anti-carves and makes opening become big then, is that TEOS is that the space between the Al bar is filled in the deposit of presoma then.Along with the development of technology, for for metal wire separation>0.35um, depth-width ratio<2: 1 often adopts PECVD/SACVD (plasma auxiliary chemical vapor deposition/inferior normal pressure chemical vapor deposition)/PECVD method, SiO before this 2Deposit, be the SACVD deposit of Ozone (ozone)-TEOS then because SACVD has good porefilling capability, but the film quality of SACVD preparation is very poor, has the disadvantageous tensile stress of subsequent technique, so need SiO for the second time 2Deposit, form " sandwich " structure.Along with the development of integrated circuit technique, the size of post-channel interconnection is also more and more littler, and when metal wire separation during less than 0.25um, most of known filling perforation methods all can not satisfy.High-density plasma chemical vapor deposition (HDP CVD) is introduced into and solves this technical problem.
High-density plasma (HDP), its ionization level are 100 times of common PECVD, are about 0.1-10%, and the more general PECVD of mean free path is long, and air pressure is very low during deposit, is millitorr (mTorr) rank.HDP CVD compares with common PECVD, and be in one of main distinction of cavity: HDP CVD not only has the plasma source of capacitance coupling type, also have ICP (inductance coupling high) thus the plasma source of mode comes ionization of gas to improve ionization level.The incidence angle of traditional PECVD when deposit because between metal wire is bigger than the bottom, makes that the speed of growth of metal top is faster than the bottom, under the bigger situation of depth-width ratio, can cause the porefilling capability deficiency, forms the cavity between metal wire.HDP CVD has two parts to combine when carrying out deposit to form: deposit, sputter.Deposit relies on chemical gas to carry out chemical reaction exactly, such as silane, and oxygen etc.Sputter is meant that the inert gas ion of ionization obtains energy and bombards the medium that is deposited on the metal under the effect of bias field.For this structure of HDPCVD is to carry out when these two steps are carried out in same cavity, on one side deposit, sputter on one side, thereby the speed of growth of control metal bottom and head.Deposit and sputter have a ratio, are referred to as the D/S ratio.For the big structure of depth-width ratio, adopt less D/S usually, the lacking of deposit just, sputter many.Film after the deposit may be different at the thickness of the zones of different of silicon chip, and to 9 measurement monitoring of silicon chip employing thickness of 8 inches, the more little then uniformity of the thickness difference of zones of different film is good more usually.For HDP CVD, uniformity was bad after less D/S can make thin film deposition usually.HDP CVD equipment vendor generally is company of Applied Materials (AppliedMaterials) and U.S. Nuo Fa company (Novellus).
In common Al technology, after the Al etching is intact, carry out Gapfill (joint filling) with HDP CVD, be with TEOS[Si (OC then 2H 5) 4] as presoma, adopt PECVD deposit SiO 2After the HDP CVD deposit, silicon chip surface remains " being uneven ", and TEOS PECVD has pair silicon chip surface to carry out planarization on the one hand, and TEOS PECVD cost is cheap more many than HDP on the other hand.Film after the TEOS PECVD deposit has a characteristic, and that is exactly a thick middle, and both sides are thin.After the TEOS deposit, and then being CMP (cmp), is exactly photoetching and the etching of Via (through hole) after the CMP
Along with the development of technology, the size of Via is more and more littler, and Via 1 in this process node of 0.18um (through hole 1) normally about 0.25um, adopts DUV (deep UV) photoetching.It is exactly DOF (depth of focus) that an important index is arranged in the photoetching, the molecule of whole photoresist just, no matter be near the photoresist surface portion or near the silicon chip part, and can both be in the depth of focus, thus fully exposure.Because the depth of focus of DUV photoetching is less, so require film flat as far as possible, also is that the uniformity of film will be got well.
After the Al etching, through HDP CVD filling perforation, it is uneven that silicon chip surface can become, and TEOSPECVD can have the effect of certain planarization to silicon chip, yet be to be nowhere near for photoetching, needs to adopt CMP to come silicon chip surface is carried out grinding of overall importance.Usually, the uniformity of film is poor before than CMP after the CMP.Therefore,, can directly cause the uniformity variation of CMP rear film, thereby make photoetching process be difficult to control if the uniformity of film is very poor before the CMP.
Another bad problem of uniformity of film be when the Via etching in.Because the Via etching adopts EPD (end point detect-terminal point detects) very difficult, what adopt usually is that etch period is controlled etching process.If the uniformity of film is bad before the etching, some places are thick, and some places are thin, can cause problems such as etching is excessive or very few.Etching is very few, can make through hole not open, and makes the metal of the upper and lower to connect, and causes Yield loss (decrease in yield).Etching is excessive, then can make when follow-up tungsten deposit WF 6(tungsten hexafluoride) and reactive aluminum make reliability be affected, and the electromigration characteristic of Al is worsened.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of process of improving film uniformity before chemical mechanical grinding, to improve the uniformity of CMP rear film, improves the rate of finished products of product.
Technical scheme of the present invention is:
1) with high-density plasma assistant chemical vapor deposition (HDP CVD) silicon dioxide, adjust the silane flow rate deposition parameters on HDP CVD cavity wall and top, wherein, the SiH on cavity top 4The flow that on original basis, reduces and the SiH of sidewall 4The flow that increases on original basis equates;
2) with the tetraethyl orthosilicate be presoma using plasma assistant chemical vapor deposition (PECVD) silicon dioxide.
The silane flow rate deposition parameters on described adjustment HDP CVD cavity wall and top comprises: the SiH on cavity top 4On original basis, reduce 1-4sccm, the SiH of sidewall 4Increase 1-4sccm on original basis, deposit air pressure is 5-10mT, and oxygen flow is at 200-300sccm, and cavity top radio-frequency power is 3700-4300w, and the sidewall radio-frequency power is 1500-2100w, and the biasing radio-frequency power is 2600-3400w.
Technique effect of the present invention is, compared with prior art, because the deposition parameters of HDP CVD is adjusted, thereby make with TEOS to be that presoma adopts the silica membrane of PECVD to be complementary, guaranteed in the middle of the preceding film of CMP and the consistency of outer ring thickness, improve the uniformity of film before the CMP, thereby created the good premise condition for the CMP cmp.
Description of drawings
Fig. 1 is the HDP CVD schematic cross-section of silicon chip thickness afterwards;
Fig. 2 is process parameter adjustment, the schematic cross-section of silicon chip thickness after the HDP CVD;
Fig. 3 is the T EOS PECVD schematic cross-section of silicon chip thickness afterwards;
Fig. 4 is the schematic cross-section of silicon chip thickness after HDP and TEOS PECVD superpose;
Fig. 5 is for adjusting back HDP CVD and the TEOS PECVD stack schematic cross-section of silicon chip thickness afterwards;
Fig. 6 is a HDP CVD cavity schematic diagram.
Embodiment
Below in conjunction with specific embodiment the present invention is elaborated.
As Fig. 1, the tendency of silicon chip film is the silicon chip thick middle after the HDP deposit before not carrying out parameter adjustment, and inner ring is thin, and the outer ring is thick, if in the middle of usually after the HDP deposit and the consistency of thickness of outer ring, then can think its uniformity difficulty the space of optimization is arranged.As Fig. 3, owing to adopt the PECVD (plasma auxiliary chemical vapor deposition) of TEOS (tetraethyl orthosilicate) usually, generally be the silicon chip thick middle as presoma, the outer ring is thin, and inner ring takes second place.The stack of HDP CVD and TEOS PECVD deposit rear film can make that then the preceding uniformity of film of CMP is poor, both shown in Figure 4, and the result after Fig. 1 and Fig. 3 stack is more high than the outer ring in the middle of the silicon chip just.
As Fig. 2, be that the reacting gas during HDP CVD is SiH through silicon chip film after the HDP deposit of parameter adjustment 4, O 2, in conjunction with Fig. 6, distributing by the silane flow rate of adjusting sidewall and top makes that the centre of film is thinner than the outer ring after the deposit, the film that can go out with the TEOS PECVD deposit after shown in Figure 3 is complementary like this.Optimal parameter is: on original sidewall-silane flow rate basis as (32-36sccm) reduce 1 or 2sccm, (as 7-9sccm) increase by 1 or 2sccm on top-silane flow rate basis, the amount of the two increase and minimizing equates, air pressure during deposit maintains 5 or 7mT, deposit cavity top radio-frequency power is 3900 or 4100w, the sidewall radio-frequency power is 1700 or 1900w, and the biasing radio-frequency power is 2900 or 3100w, and the flow of oxygen is 240 or 260sccm during deposit.Therefore, by regulating the HDP deposition parameters, make film behind the HDP CVD at the silicon chip center than thin edge, thereby and TEOS PECVD be complementary, reach and improve the uniformity of improving thin film deposition before the CMP, its effect as shown in Figure 5.
The present invention is applicable to numerous HDP equipment (as the Ultima of company of Applied Materials, Ultima+ etc.), and TEOS PECVD also is applicable to the equipment of various models.

Claims (5)

1, a kind of process of improving film uniformity before chemical mechanical grinding is characterized in that: may further comprise the steps:
1) with high-density plasma assistant chemical vapor deposition silicon dioxide, adjust the cavity wall of high-density plasma assistant chemical vapor deposition and the silane flow rate deposition parameters on top, wherein, the SiH on cavity top 4The flow that on original basis, reduces and the SiH of sidewall 4The flow that increases on original basis equates;
2) with the tetraethyl orthosilicate be presoma using plasma assistant chemical vapor deposition silicon dioxide.
2, the process of improving film uniformity before chemical mechanical grinding according to claim 1 is characterized in that: the reacting gas of described high-density plasma assistant chemical vapor deposition is SiH 4(silane), O 2(oxygen).
3, the process of improving film uniformity before chemical mechanical grinding as claimed in claim 1 or 2, it is characterized in that: the described the 1st) Bu deposition parameters comprises: the SiH on cavity top 4Flow, the SiH of sidewall 4Flow, deposit air pressure, oxygen flow, cavity top radio-frequency power, sidewall radio-frequency power and biasing radio-frequency power, the SiH on cavity top 4The flow that on original basis, reduces and the SiH of sidewall 4The flow that increases on original basis is 1-4sccm.
4, the process of improving film uniformity before chemical mechanical grinding according to claim 3, it is characterized in that: deposit air pressure is 5-10mT, oxygen flow is at 200-300sccm, cavity top radio-frequency power is 3700-4300w, the sidewall radio-frequency power is 1500-2100w, and the biasing radio-frequency power is 2600-3400w.
5. the process of improving film uniformity before chemical mechanical grinding according to claim 1 is characterized in that the range of application of described process can be employing aluminium as interconnecting metal.
CNB2005100294010A 2005-09-02 2005-09-02 Process capable of improving film uniformity before chemical mechanical grinding Expired - Fee Related CN100530563C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB2005100294010A CN100530563C (en) 2005-09-02 2005-09-02 Process capable of improving film uniformity before chemical mechanical grinding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2005100294010A CN100530563C (en) 2005-09-02 2005-09-02 Process capable of improving film uniformity before chemical mechanical grinding

Publications (2)

Publication Number Publication Date
CN1925117A CN1925117A (en) 2007-03-07
CN100530563C true CN100530563C (en) 2009-08-19

Family

ID=37817683

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005100294010A Expired - Fee Related CN100530563C (en) 2005-09-02 2005-09-02 Process capable of improving film uniformity before chemical mechanical grinding

Country Status (1)

Country Link
CN (1) CN100530563C (en)

Also Published As

Publication number Publication date
CN1925117A (en) 2007-03-07

Similar Documents

Publication Publication Date Title
US6252303B1 (en) Intergration of low-K SiOF as inter-layer dielectric
US6211040B1 (en) Two-step, low argon, HDP CVD oxide deposition process
US7297640B2 (en) Method for reducing argon diffusion from high density plasma films
CN100423208C (en) Dielectric etch method with high source and low bombardment plasma providing high etch rates
US20060091431A1 (en) Contact plug processing and a contact plug
JPH0669192A (en) Manufacture of semiconductor device
JP2001244337A (en) Method and apparatus for forming film on substrate
CN102693931A (en) Thin film filling method
CN104658964B (en) The forming method of through hole
JP2001168193A (en) LOW k DIELECTRIC COMPOSITE MATERIAL LAYER FOR INTEGRATED CIRCUIT STRUCTURE THAT OFFERS VOID-FREE LOW k DIELECTRIC MATERIAL BETWEEN METAL LINES WHILE RELAXING VIA POISONING
CN1831190A (en) Method for preventing metals from being damaged by high density plasma chemical vapor deposition
US6291030B1 (en) Method for reducing capacitance in metal lines using air gaps
US6607992B2 (en) Antireflection coating and semiconductor device manufacturing method
KR20040038606A (en) Method for forming integrated dielectric layers
CN103633014A (en) Method of manufacturing semiconductor device
US7271110B2 (en) High density plasma and bias RF power process to make stable FSG with less free F and SiN with less H to enhance the FSG/SiN integration reliability
US6780731B1 (en) HDP gap-filling process for structures with extra step at side-wall
CN101017794A (en) A method for sealing the small hole of the multi-hole low dielectric material in the Damascus structure
CN100530563C (en) Process capable of improving film uniformity before chemical mechanical grinding
US6864150B2 (en) Manufacturing method of shallow trench isolation
WO2022021677A1 (en) Wafer bonding structure, wafer bonding method and chip bonding structure
CN102024696A (en) Opening and forming method thereof
US7446061B2 (en) Method of forming insulating film, method of manufacturing semiconductor device and their controlling computer program
US7052970B2 (en) Method for producing insulator structures including a main layer and a barrier layer
CN102354684A (en) Wiring structure forming method

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090819

Termination date: 20170902

CF01 Termination of patent right due to non-payment of annual fee