CN100499093C - Chip packaging structure - Google Patents
Chip packaging structure Download PDFInfo
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- CN100499093C CN100499093C CN 200610099222 CN200610099222A CN100499093C CN 100499093 C CN100499093 C CN 100499093C CN 200610099222 CN200610099222 CN 200610099222 CN 200610099222 A CN200610099222 A CN 200610099222A CN 100499093 C CN100499093 C CN 100499093C
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- chip
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- confluxes
- frame
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 39
- 239000000084 colloidal system Substances 0.000 claims abstract description 15
- 238000012856 packing Methods 0.000 claims description 13
- 238000000034 method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 235000019994 cava Nutrition 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 239000012945 sealing adhesive Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Abstract
A chip packaging structure comprises a chip, a lead frame, a plurality of weld lines and a packaging colloid. Wherein, the chip is provided with a positive surface and a plurality of connecting gaskets arranged on one side of the positive surface. The chip is fixed below the lead frame. The lead frame is provided with a plurality of first inner pins and a plurality of second inner pins. These first inner pins are positioned on the positive surface. In addition, an end of each first inner pin and each second inner pin is arranged peripherally in these connecting gaskets. These weld lines are respectively connected between the first inner pin and the connecting gasket and between the second inner pin and the connecting gasket. The chip, the first inner pin, the second inner pin and the weld line are wrapped by the packaging colloid. For the connecting gasket is positioned on one side of the positive surface, rate of collapsed weld line is reduced.
Description
Technical field
The invention relates to a kind of chip-packaging structure, and particularly relevant for a kind of chip-packaging structure (CHIP PACKAGE STRUCTURE) with lead frame.
Background technology
In semiconductor industry, (integrated circuits, production IC) mainly can be divided into three phases to integrated circuit: the encapsulation (IC package) of the making (ICprocess) of the design of integrated circuit (IC design), integrated circuit and integrated circuit.
In the making of integrated circuit, chip (chip) is to finish via wafer (wafer) making, formation integrated circuit and cutting crystal wafer steps such as (wafer sawing).Wafer has an active surface (active surface), the surface with active member (active device) of its general reference wafer.After the integrated circuit of wafer inside was finished, the active surface of wafer more disposed a plurality of weld pads (bonding pad), can outwards be electrically connected at a carrier (carrier) via these weld pads so that finally cut formed chip by wafer.Carrier for example is a lead frame (leadframe) or a base plate for packaging (package substrate).Can the go between mode of bonding (wire bonding) or flip-chip bonded (flip chip bonding) of chip is connected on the carrier, makes these weld pads of chip can be electrically connected at the contact of carrier, to constitute a chip-packaging structure.
Fig. 1 is the generalized section of existing chip encapsulating structure.Please refer to Fig. 1, chip-packaging structure 100 is that (it comprises a chip 110, a lead frame 120, many bonding wires 130 and a packing colloid 140 to a kind of lead foot for lead on chip, chip-packaging structure LOC) on chip.Chip 110 comprises a plurality of connection pads 112, and wherein these connection pads 112 are positioned on the active surface 110a of chip 110, and these connection pads 112 are positioned at the middle section of active surface.Lead frame 120 has many interior pins 122, and wherein pin 122 is to be positioned on the active surface 110a in these, and arranges along the periphery of active surface 110a.Bonding wire 130 is disposed between connection pad 112 and the interior pin 122, with pin 122 in connection pad 112 is electrically connected at.140 of packing colloids are coated on chip 110, interior pin 122 and bonding wire 130 in it.
Because pins 122 are to arrange along chip 110 peripheries in these, so the length of these bonding wires 130 is longer, and cave in easily and cause electrical short circuit.In addition, because the length of these bonding wires 130 is longer, therefore the liquid packing colloid 140 that these bonding wires 130 are also poured in the mould easily when forming packing colloid 140 is pulled apart and is caused electrically and open circuit.Be with, with regard to packaging technology, the design of existing chip encapsulating structure 100 causes the product yield low easily.
Summary of the invention
Purpose of the present invention just is to provide a kind of chip-packaging structure, to reduce the probability that bonding wire caves in.
The present invention proposes a kind of chip-packaging structure, and it comprises a chip, a lead frame, many bonding wires and a packing colloid.Chip has an active surface and a plurality of connection pads that are disposed on the active surface, and these connection pads are positioned at the same side of active surface.Chip is bonded to the lead frame below.Pin and many second interior pins in lead frame has many first, wherein these first interior pins are positioned on the active surface, and the second interior pin is positioned at the chip outside, and is adjacent to first connection pad.An end of pin and each bar second interior pin is positioned at the periphery of these connection pads in each bar first.Lead frame has more at least one first frame and at least one second frame that confluxes that confluxes, lay respectively between the first interior pin and first connection pad, and in second between pin and first connection pad, wherein first confluxes chord position on active surface, and second conflux chord position outside chip.These bonding wires are connected between the first interior pin and the connection pad, and between the second interior pin and the connection pad.Packing colloid is coated on pin and bonding wire in the pin, second in the chip, first in it.
In an embodiment of the present invention, the second interior pin and chip can also be coplines.In an embodiment of the present invention, second confluxes can keep a difference in height between the pin in frame and these second, and second frame that confluxes is put (down-set) design for heavy.In addition, chip-packaging structure more can comprise at least one second bonding wire and at least one the 3rd bonding wire, and chip has more at least one second connection pad, second connection pad and these first connection pads are positioned at the same side of active surface, second bonding wire connects second connection pad and first and confluxes between the frame, and the 3rd bonding wire connects first and confluxes frame and these first interior pins between one of them.In addition, chip-packaging structure can also more comprise at least one the 4th bonding wire and at least one the 5th bonding wire, and chip has more at least one the 3rd connection pad, the 3rd connection pad and these first connection pads are positioned at the same side of active surface, the 4th bonding wire connects the 3rd connection pad and second and confluxes between the frame, and the 5th bonding wire connects second and confluxes frame and these second interior pins between one of them.
The present invention be make connection pad on the chip be positioned at the same side of active surface, with first pin configuration on active surface and make an end of each bar first pin and second pin be positioned at the periphery of these connection pads, so the present invention can reduce interior pin (promptly first in the pin and the second interior pin) and connection pad between distance.Be to shorten the line length that is connected in the bonding wire between connection pad and the interior pin, and then reduce the probability that bonding wire caves in the present invention.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is the generalized section of existing chip encapsulating structure.
Fig. 2 is the generalized section of the chip-packaging structure of one embodiment of the invention.
Fig. 3 is the schematic diagram of manufacture method of the chip-packaging structure of one embodiment of the invention.
Fig. 4 is the generalized section of the chip-packaging structure of one embodiment of the invention.
Fig. 5 illustrates the schematic diagram into the chip-packaging structure of one embodiment of the invention.
100: chip-packaging structure
110: chip
110a: active surface
112: connection pad
120: lead frame
122: interior pin
130: bonding wire
140: packing colloid
200: chip-packaging structure
200 ': chip-packaging structure
200 ": chip-packaging structure
210: chip
212: active surface
214: the first connection pads
216: the second connection pads
218: the three connection pads
220: lead frame
220a: pin in first
220b: pin in second
222: the first framves that conflux
224: the second framves that conflux
230: the first bonding wires
232: the second bonding wires
234: the three bonding wires
236: the four bonding wires
238: the five bonding wires
240: packing colloid
Embodiment
Fig. 2 is the generalized section of the chip-packaging structure of one embodiment of the invention.Please refer to Fig. 2, chip-packaging structure 200 comprises a chip 210, a lead frame 220, many first bonding wires 230 and a packing colloid 240.Chip 210 has an active surface 212 and a plurality of first connection pads 214 that are disposed on the active surface 212, and these first connection pads 214 are positioned at a side of active surface 212.In more detail, these first connection pads 214 are sides that are adjacent to active surface 212.
These first bonding wires 230 are connected between the first interior pin 220a and first connection pad 214, and between the second interior pin 220b and first connection pad 214.Packing colloid 240 is coated on the pin 220b and first bonding wire 230 in chip 210, the first interior pin 220a, second in it.
Though in Fig. 2, pin 220b all is positioned on the active surface 212 in the first interior pin 220a and second, Fig. 2 and corresponding explanation are not in order to limit the present invention.In other embodiments of the invention, the second interior pin 220b more can be positioned at the outside of chip 210.
Please refer to Fig. 3, it is the schematic diagram of manufacture method of the chip-packaging structure of one embodiment of the invention.Chip 210 at first is provided.Then, a lead frame that does not cut as yet 220 is disposed on the active surface 212 of chip 210, wherein first of this lead frame that does not cut the as yet 220 interior pin 220a is disposed on the active surface 212, and the second interior pin 220b is disposed at outside the chip 210.In addition, the end of pin 220b is the periphery that is positioned at first connection pad 214 in the first interior pin 220a and second, and second interior pin 220b and chip 210 coplines.Then, cut technology via lead key closing process, sealing adhesive process and to what the lead frame 220 that does not cut as yet carried out in regular turn, to form the chip-packaging structure 200 ' of Fig. 4, wherein Fig. 4 is the generalized section of the chip-packaging structure of one embodiment of the invention.For the convenience on illustrating, Fig. 4 is the schematic diagram of perspective packing colloid 240.In Fig. 4, first bonding wire 230 of part is to be electrically connected between the first interior pin 220a and first connection pad 214, and remaining 230 of first bonding wire is to be electrically connected between the second interior pin 220b and first connection pad 214.
It should be noted that, in above-mentioned configuration mode, because pin 220a is disposed on the active surface 212 in first, pin 220b is disposed at outside the chip 210 in second, and the end of the pin 220a and the second interior pin 220b is the periphery that is positioned at first connection pad 214 in first, therefore present embodiment can shorten the distance of the first interior pin 220a and first connection pad 214 compared to existing technologies, and the distance that shortens the second interior pin 220b and first connection pad 214.
In addition, chip 210 more can have at least one second connection pad 216 and at least one the 3rd connection pad 218, and wherein second connection pad 216 can be ground connection connection pad or power supply connection pad, and the 3rd connection pad 218 can be ground connection connection pad or power supply connection pad.It should be noted that first connection pad 214, second connection pad 216 and the 3rd connection pad 218 are the same sides that are positioned at active surface 212.
When chip 210 had at least one second connection pad 216 and at least one the 3rd connection pad 218, chip-packaging structure 200 ' more can have at least one the second bonding wires 232, at least one the 3rd bonding wire 234, at least one the 4th bonding wire 236 and at least one the 5th bonding wire 238.In addition, lead frame 220 more can have at least one first frame 222 and at least one second frame 224 that confluxes that confluxes.First frame 222 that confluxes is positioned on the active surface, and in first between pin 220a and first connection pad 214.Second frame 224 that confluxes is positioned at outside the chip 210, and in second between pin 220b and first connection pad 214.
Thus, present embodiment just can be connected in second connection pad 216 and first with second bonding wire 232 and conflux between the frame 222, and the 3rd bonding wire 234 is connected in first confluxes in frame 222 and these first pin 220a between one of them.In addition, present embodiment can be connected in the 3rd connection pad 218 and second with the 4th bonding wire 236 and conflux between the frame 224, and the 5th bonding wire 238 is connected in second confluxes in frame 224 and these second pin 220b between one of them.Thus, present embodiment just can make the easier execution of lead key closing process that forms bonding wire (i.e. first bonding wire 230, second bonding wire 232, the 3rd bonding wire 234, the 4th bonding wire 236 and the 5th bonding wire 238) via first frame 222 and second frame 224 that confluxes that confluxes.
In addition, in one embodiment of this invention, second confluxes more can have a difference in height between the frame 224 and the second interior pin 220b.Please refer to Fig. 5, it illustrates the schematic diagram into the chip-packaging structure of one embodiment of the invention.Chip-packaging structure 200 " be similar to chip-packaging structure 200 ', wherein difference between the two mainly is chip-packaging structure 200 " second conflux frame 224 be in the heavy mode that installs come with the second interior pin 220b between keep a difference in height.Thus, present embodiment not only can be simplified the complexity of lead key closing process via second frame 224 that confluxes, and more can shorten the spacing between the pin 220b and chip 210 in second via the heavy mode that installs meter.
Compared to existing technology, because connection pad of the present invention is the same side, first pin that are positioned at active surface is to be disposed on the active surface and an end of each bar first pin and second pin is the periphery that is positioned at these connection pads, so the present invention can reduce the distance between interior pin (i.e. the first interior pin and the second interior pin) and the connection pad.Be with short bonding wire interior pin to be electrically connected at corresponding connection pad with the present invention.
Hold above-mentionedly, because the length of bonding wire shortened, so the present invention can reduce the probability that bonding wire caves in, and the probability that bonding wire is torn when reducing liquid packing colloid and being poured in the mould.It is the yield of the Chip Packaging body technology that can improve with structural design of the present invention.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim person of defining.
Claims (5)
1. chip-packaging structure is characterized in that it comprises:
One chip have an active surface and a plurality of first connection pads that are disposed on this active surface, and those first connection pads is positioned at the same side of this active surface;
One lead frame, chip is bonded to this lead frame below, and pin and many second interior pins in this lead frame has many first, wherein those first interior pins are positioned on this active surface, those second interior pins are positioned at this chip outside, and be adjacent to those first connection pads, respectively this in first pin with respectively this in second an end of pin be positioned at the periphery of those first connection pads, this lead frame has more at least one first frame and at least one second frame that confluxes that confluxes, lay respectively between those first interior pins and those first connection pads, and between those second interior pins and those first connection pads, wherein this first confluxes chord position on this active surface, and this second confluxes chord position in this chip outside;
Many first bonding wires connect respectively between those first interior pins and those first connection pads, and between those second interior pins and those first connection pads; And
One packing colloid coats this chip, those first interior pins, those second interior pin and those first bonding wires.
2. chip-packaging structure according to claim 1, it is characterized in that wherein those in second pins and this chip be copline.
3. chip-packaging structure according to claim 1, it is characterized in that more comprising at least one second bonding wire and at least one the 3rd bonding wire, and this chip has more at least one second connection pad, this second connection pad and those first connection pads are positioned at the same side of this active surface, this second bonding wire connects this second connection pad and this first and confluxes between the frame, and the 3rd bonding wire connects this and first confluxes in frame and those first pin between one of them.
4. chip-packaging structure according to claim 3, it is characterized in that more comprising at least one the 4th bonding wire and at least one the 5th bonding wire, and this chip has more at least one the 3rd connection pad, the 3rd connection pad and those first connection pads are positioned at the same side of this active surface, the 4th bonding wire connects the 3rd connection pad and this second and confluxes between the frame, and the 5th bonding wire connects this and second confluxes in frame and those second pin between one of them.
5. chip-packaging structure according to claim 3 is characterized in that wherein this second confluxes and keep a difference in height between the pin in frame and those second, and this second frame that confluxes is the heavy meter that installs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610099222 CN100499093C (en) | 2006-07-21 | 2006-07-21 | Chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610099222 CN100499093C (en) | 2006-07-21 | 2006-07-21 | Chip packaging structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101110399A CN101110399A (en) | 2008-01-23 |
| CN100499093C true CN100499093C (en) | 2009-06-10 |
Family
ID=39042382
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200610099222 Active CN100499093C (en) | 2006-07-21 | 2006-07-21 | Chip packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100499093C (en) |
-
2006
- 2006-07-21 CN CN 200610099222 patent/CN100499093C/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN101110399A (en) | 2008-01-23 |
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Address after: 9688 Songze Avenue, Qingpu Industrial Zone, Shanghai Co-patentee after: ChipMOS Technologies (Bermuda) Ltd. Patentee after: UNIMOS MICROELECTRONICS(SHANGHAI) Ltd. Address before: 201700 No. 9688 Songze Avenue, Qingpu Industrial Zone, Shanghai Co-patentee before: ChipMOS Technologies (Bermuda) Ltd. Patentee before: ChipMOS Technologies (Shanghai) Co.,Ltd. |
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| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20190718 Address after: 9688 Songze Avenue, Qingpu Industrial Zone, Shanghai Co-patentee after: ChipMOS Technologies Inc. Patentee after: UNIMOS MICROELECTRONICS(SHANGHAI) Ltd. Address before: 201700 No. 9688 Songze Avenue, Qingpu Industrial Zone, Shanghai Co-patentee before: ChipMOS Technologies (Bermuda) Ltd. Patentee before: UNIMOS MICROELECTRONICS(SHANGHAI) Ltd. |