CN100479158C - 沿多个表面具有应变晶格结构的fet沟道 - Google Patents

沿多个表面具有应变晶格结构的fet沟道 Download PDF

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CN100479158C
CN100479158C CNB2004800210466A CN200480021046A CN100479158C CN 100479158 C CN100479158 C CN 100479158C CN B2004800210466 A CNB2004800210466 A CN B2004800210466A CN 200480021046 A CN200480021046 A CN 200480021046A CN 100479158 C CN100479158 C CN 100479158C
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raceway groove
lattice structure
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CN1826690A (zh
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拉齐夫·V·约什
理查德·Q·威廉姆斯
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Abstract

一种FinFET(10)的沟道(16)，它具有沟道核心(24)和沟道外壳(32)，各由确定不同晶格结构的半导体材料组成，以便利用应变硅的性质。栅通过栅介质被耦合到沟道外壳。示例性材料是Si和SixGe1-x，其中78＜x＜92。沟道核心(24)具有宽度为wc的顶部表面(26)和高度为hc的直立表面(28，30)，优选彼此取向成90度。沟道外壳(32)与顶部表面(26)和直立表面(28，30)相接触，致使与仅仅沿顶部表面(26)的接触相比，增大了界面面积，改善了导电性和栅(18)对沟道(16)的控制。为了能够在稳定的SRAM中得到尺寸更小的FET(10)，可以调整高度hc。公开了各种形成沟道(16)的方法，包括掩蔽和腐蚀方法、处置晶片/载体晶片方法、以及浅沟槽方法。公开了具有一个到四个栅的FinFET的实施方案和方法。

Description

沿多个表面具有应变晶格结构的FET沟道
技术领域
此技术一般涉及到设置在半导体晶片或芯片上的场效应晶体管(FET)，确切地说是涉及到作为连接FET源与漏的沟道的层状结构，其中各个层中一个层的特征在于应变的晶格结构。
背景技术
半导体和集成电路芯片由于其成本和尺寸不断降低而已经在许多产品中变得随处可见。小型化通常能够在更低的功率电平和更低的成本下提高性能(单位时间内的处理次数更多且产生的热更少)。目前的技术处于或接近诸如逻辑门、FET、电容器之类的某些微器件的原子级尺寸。具有成千上万这种器件的电路芯片并不罕见。而且，尺寸的减小看来接近了埋置在其半导体衬底上以及埋置在其半导体衬底内的轨线和微器件的物理极限。本发明的目标就是这种微尺寸的FET器件。FET是一种由源、栅、漏组成的晶体管。FET的作用依赖于多数载流子沿源与漏之间的越过栅行进的沟道的流动。通过源与漏之间的沟道的电流，由栅下方的横向电场来控制。可以用一个以上的栅来更有效地控制沟道。栅的长度决定了FET转换的快慢以及电路所能够工作的速度，且通常大约与沟道的长度(亦即源与漏之间的距离)相同。目前现有技术的栅长度约为50nm，并在下一个10年内正向10nm推进。这种尺寸的减小应该能够在单个芯片上得到10亿个以上的器件。但这种小尺寸要求对诸如短沟道效应、穿通、以及MOS泄漏电流之类的性能问题进行更严格的控制。
通过使用一个或多个称之为鳍的鳍形沟道，新近已经成功地减小了FET的尺寸。采用鳍的FET被称之为FinFET。先前，互补金属氧化物半导体(CMOS)器件除了FET栅被设置在沟道顶部上之外，基本上沿半导体衬底表面是平坦的。鳍利用垂直结构突破了这一范例，以便尽量增大暴露于栅的沟道表面积。由于栅延伸在鳍形沟道的3个侧面上而不是仅仅跨越更传统的平坦沟道的顶部，故栅对沟道的控制更强。是为具有6个鳍的现有技术FET的TEM显微照片的图1，示出了FinFET的一个例子。各个成对的鳍包含NFET和PFET。
提高鳍性能的一种方法是在不同材料的层中形成鳍。在美国专利No.6252284 B1“Planarized Silicon Fin Device”中，描述了一种受让于本发明受让人的用来控制短沟道效应的示例性器件。
多层平整FET鳍中多个层之一常常是应变硅。先前已经发现，对硅的晶格结构进行双轴拉伸，能够加速电子通过晶体管的流动，从而提高性能并降低功耗。不同层中的原子有一种自然的倾向，即借助于沿失配的平坦界面拉伸和/或压缩其失配的晶格结构而彼此对准。改变各个材料的厚度和化学组成，有助于控制各个材料中的延伸和压缩程度。作为一个例子，图2不按比例地示出了天然(未被拉伸)状态下的硅晶格和锗晶格。当硅被设置(或生长)在较厚的锗层上时，如在图2b的SiGe化合物中那样，硅的晶格拉伸而锗的晶格基本上保持不变，得到应变硅。由于锗层相对地较大的厚度产生了较大的结构完整性和对压缩的较大阻力，故得到了这一结果。晶格拉伸的实际过程也可以引起Si和Ge的原子在晶格结构内相互混合。这使二种原子汇集在单个层内，其中，与天然(未被拉伸的)硅晶格结构相比，较大的Ge原子强迫汇集的晶格结构发生拉伸。还可能实现与图2b所示相反的效应，其中，较薄的锗层当被键合到较厚的硅层时，呈现出晶格压缩。在NFET中，应变硅已经显示出直至70％的电子/空穴迁移率提高，而在PFET中，已经显示出直至30％的电子/空穴迁移率提高。诸如硅锗碳之类的其它材料也可以被用来形成提高导电性的结晶异质结构。存在着几种用来形成应变层的方法，包括化学气相淀积(CVD)和分子束外延(MBE)。
沿平面设置的应变硅已经被用于现有技术的FinFET中。但电流泄漏一直是进一步向原子极限缩小FET的一个限制因素。由于通常伴随沟道长度的长度较短的FET栅对电荷载流子(空穴或电子)的控制能力较小，故随着小型化的进展，电流泄漏成了一个日益重要的关切。
晶体管被关断时的非有意电荷载流子流动，被称为“电流泄漏”。电流泄漏是待机晶体管消耗功率的主要来源。电流泄漏可以被分为二种类型：MOS关断电流和栅隧穿泄漏电流，在MOS关断电流中，非有意电流通过沟道而不管栅是否试图完全切断电流，在栅隧穿泄漏电流中，非有意电流跟随寄生路径流动，流入到沟道中、扩散区中、或硅本体中。随着FET沟道长度不断地减小，栅隧穿泄漏电流有望成为设计者的重要关切。鳍结构增强了栅对沟道的控制，但栅对电流的控制不是无限制的，即使在现有技术的FinFET中也是如此。综合电流泄漏问题，小型化使得能够得到甚至更低的功率水平，而这要求更绝对的栅控制。逃脱栅控制的电流泄漏更不容易区别于有意电流，特别是在低电流电平下更是如此。
所需要的是一种具有提高了的NFET和PFET性能的能够按比例缩小的FET。此FET优选应该改善鳍结构中的栅控制，显示出提高了的载流子输运性质。
发明内容
根据这些论述的本优选实施方案，克服了上述和其它的问题，并实现了其它的一些优点。本发明涉及到用来电连接场效应晶体管(FET)的源与漏的沟道，通常称为FinFET的鳍。此沟道包括沟道核心和沟道外壳(channel envelope)。沟道核心被耦合到诸如SIMOX晶片(具有被注入氧分隔开的上部区域的晶片)或键合晶片之类的衬底。沟道核心确定了分隔于衬底的顶部表面以及衬底与顶部表面之间的相反的侧面。沟道核心由确定第一晶格结构的第一半导体材料组成。
沟道外壳与沟道核心的相反的侧面以及顶部表面相接触。沟道外壳由确定不同于第一晶格结构的第二晶格结构的第二半导体材料组成。晶格结构的这一差异由于晶格结构的拉伸或压缩而提供了增强的导电性。此二种材料优选为硅和硅锗化合物。
在本发明的另一情况下，沟道核心确定了顶部表面和邻接的侧面。在一个优选实施方案中，顶部表面是水平顶部，而侧面是沟道核心二个直立侧壁之一，但可以采用二个从衬底延伸且会合于顶峰处的二个直立表面或由第三横向表面连接的二个侧壁。沟道核心包含第一半导体材料，而沟道外壳包含不同于第一半导体材料的第二半导体材料。至少第一或第二半导体材料之一由于拉伸或压缩晶格结构之一而显示出提高了的导电性。沟道外壳与顶部表面和侧面相接触，与仅仅沿顶部表面提供界面的现有技术的沟道相比，提供了不同晶格材料之间更大的界面面积。上述的示例性材料可用来提供拉伸的或压缩的晶格结构。
本发明还包括制作FET沟道的方法。在一种方法中，衬底被提供成具有第一半导体材料的重叠层。例如，利用掩蔽和腐蚀技术，第一沟道核心由重叠层确定。沟道核心确定了与衬底分隔开的顶部表面以及衬底与顶部表面之间的相反的第一和第二侧壁。此方法还包括将第二半导体材料层设置成至少接触二个表面(亦即顶部表面以及第一侧壁和第二侧壁中的至少二个)。通过不同于第一半导体材料的第二半导体材料层的导电性由于其与沟道核心接触而得到提高。第二半导体材料层可以经由真空淀积来淀积，或可以被生长在载体晶片上并与之分隔开以便接触沟道核心的适当表面。
形成沟道的另一种方法包括在衬底上提供第一半导体材料层。此方法包括在上层中形成沟槽，然后由沟槽将上层分成第一区和第二区。可以用诸如TEOS(也称为四乙氧基硅烷、四乙基原硅酸盐、四乙烯基原硅酸盐、四乙氧基硅化物)之类的缓冲材料来填充此沟槽。然后清除第二区部分，留下厚度小于沟槽深度的第一半导体材料的剩余层。这暴露了部分沟槽。然后，此方法包括将第二半导体材料层设置在剩余层上邻接于沟槽。上面讨论了示例性半导体材料。剩余层优选小于大约15nm。在第二半导体材料是SixGe1-x的情况下，可以选择锗的相对浓度来促进沟道的热稳定性。锗的含量优选约为8-22％，最优选约为10-20％，且低温化学气相淀积工艺被用来形成第二半导体材料层。
而且，此处所述的是一种用来电连接场效应晶体管(FET)的源与漏的沟道，它包含沟道核心以及沟道外壳，沟道核心包含耦合到衬底的底部表面，并确定与衬底分隔开的顶部表面以及底部表面与顶部表面之间的相反的侧壁表面，其中，沟道核心由确定第一晶格结构的第一半导体材料组成，沟道外壳与顶部表面、底部表面、以及侧壁表面之一中的至少一个(或它们的组合)相接触，其中，沟道外壳包含第二半导体材料，它包含不同于第一晶格结构的应变晶格结构，此沟道外壳被电耦合到栅电极。此沟道优选由驰豫的Si-Ge晶格组成，而外壳由应变的硅晶格组成。
此处公开了采用根据本论述的FinFET的一种示例性电路SRAM电路。
附图说明
参照附图，在优选实施方案的下列详细描述中，这些论述的上述和其它的情况变得更为明显。在这些附图中：
图1是具有6个鳍的现有技术FET的TEM显微照片；
图2a和2b是现有技术图，示出了当设置成相反于其天然状态(图2a)的邻接于锗(图2b)时，硅的晶格结构的应变情况；
图3是方框图，示出了一种其中可以应用本发明的FinFET；
图4是沿图3中4’-4’线的剖面图；
图5a-5f是放大的剖面图，示出了一种利用掩蔽和腐蚀将沟道外壳淀积到沟道核心上来制作根据本发明的沟道的方法；
图6a-6h是放大的剖面图，示出了另一种利用载体晶片和处置晶片来制作至少一个沟道的方法；
图7a-7f是放大的剖面图，示出了另一种利用浅沟槽来制作PFET沟道的方法；
图8a-8f是FinFET器件各种实施方案的透视图；而
图9示出了一种SRAM电路，可用来讨论量子化。
具体实施方式
上面描述了图1和2a-2b，并用来理解本发明。图3在方框图中示出了FET 10。如本技术领域所知，源12和漏14经由被栅18跨越的沟道16被电连接。在单个FET 10中可以有一个或多个沟道16和栅18。如此处所使用的那样，沟道16的长度是从源12到漏14的距离，如图3所示。
图4示出了沟道16沿剖面线4’-4’的剖面图。FET 10被设置在诸如其上有埋置氧化物层22的硅21之类的衬底20上。沟道核心24由设置在衬底20上的第一半导体材料组成。如本技术领域所知，衬底20优选为硅基晶片，例如SIMOX晶片、键合晶片、或CZ硅晶片(用切克拉尔斯基工艺制作的硅晶片)。沟道核心优选被制作在形成部分衬底20的埋置氧化物层22的顶部上。沟道核心24确定了底部表面27(被示为附着于衬底20)、分隔于衬底20的顶部表面26、以及设置在衬底20与顶部表面26之间的相反的侧壁28和30。组成沟道核心的第一半导体材料确定了第一天然晶格结构。如此处使用的那样，除非另有说明，特定材料(元素或化合物)的天然晶格结构指的是所涉及的特定材料在其天然状态下的晶格结构，亦即未被诸如上述对应变硅那样的外部操纵而拉伸、压缩、或应变的晶格结构。显示出驰豫晶格结构的化合物此处未被描述为天然状态的晶格结构，在驰豫的晶格结构中，驰豫仅仅是由于目的在于清除可能存在的张应力或压应力而进行的退火或其它处理。
当在剖面中观察沟道16时，沟道外壳32基本上被设置在沟道核心部分24的没有直接与衬底20相接触的部分上，至少在被栅18跨越的沟道16部分处。沟道外壳32优选被耦合到沟道核心24的顶部表面26以及相反的侧壁28和30。沟道外壳32由确定不同于第一晶格结构的第二晶格结构的第二半导体材料组成。第一与第二半导体材料的不同的天然晶格结构至少在沟道核心24与沟道外壳32之间的边界处引起张应力或压应力。此处称为“异质结”的这一天然晶格的失配，方便了栅介质接触异质结叠层处的载流子输运。但载流子输运不一定要在异质结处被最大化；如本技术领域所知，依赖于各种因素，载流子输运的主沟道也可以形成在一种材料或其它不同的材料内。沟道核心24确定了核心的宽度wc和核心高度hc。同样，沟道外壳32确定了外壳宽度we和外壳高度he。可以选择这些尺寸的任何一个或全部来优化或控制相反侧壁28和30与顶部表面26的组合表面积。在沟道核心24和/或外壳32不是矩形(如此处主要所示的那样)的情况下，例如当沟道核心24是三角形且沟道外壳32被设置在沟道核心24的二侧上时，宽度和高度被认为是特定分量的平均值。可以根据第一和/或第二半导体材料的特定材料、掺杂剂在其中的存在、或核心24和外壳32的尺寸，来选择采用此处所述的本发明沟道16的FET 10的阈值电压。
对于PFET，包含沟道核心24的第一半导体材料优选是硅，而包含沟道外壳32的第二半导体材料优选是诸如Si0.7Ge0.3之类的包含硅和锗的化合物。对于NFET，包含沟道核心24的第一半导体材料优选是被处理成显示出驰豫晶格结构的包含硅和锗的化合物，而包含沟道外壳32的第二半导体材料优选是硅。
可以由多晶或金属或本技术领域所知的其它材料组成的栅18，被设置在沟道16上，以便通过设置在沟道外壳32周围的也称为栅介质的介质层33而接触沟道外壳32。介质层33可以包括氧化物、氮氧化物、或稀土氧化物(例如氧化铪)。沟道外壳32被设置为基本上防止和优选完全地防止栅18与沟道核心24之间的接触。
图5示出了用来制作根据此处所述的FET 10的一种优选方法。图5a-5f示出了一个实施方案，其中，PFET沟道34和NFET沟道36二者都被设置在同一个衬底20上。
在图5a中，提供了包括埋置氧化物层(BOX)22并层叠有诸如硅之类的第一半导体材料层18的衬底20。可以用本技术领域所知的SIMOX晶片，可以用键合晶片，或可以用切克拉尔斯基工艺提供的晶片，来提供衬底层20、BOX层22、以及第一半导体材料层38的组合。在图5b中，利用掩蔽和腐蚀，或利用本技术所知的其它方法，第一沟道核心40和第二沟道核心42由第一半导体材料层38确定。第一沟道核心40的长度和/或宽度可以不同于第二沟道核心42的长度和/或宽度。图5c示出了第二沟道核心42上以及除了第一沟道核心40紧邻之外的所有区域上的掩模44(示出了二个掩模)。腐蚀或其它所知的工艺可以被用来从与第一沟道核心40的相反的侧壁表面的接触清除掩模44，或用来防止掩模44接触这些侧壁。第一沟道核心40将成为PFET沟道34。
图5d示出了第二半导体材料46在整个晶片上的淀积。第二半导体材料层46优选是通过超高真空化学气相淀积(UHVCVD)所淀积的硅和锗的化合物，但其它化学淀积工艺也是兼容的。层46最优选将厚度确定为5-10nm，且层46的厚度决定于锗的浓度以及有关这种锗浓度的层热稳定性的标准。整个图5d在图5e中被整平，以便清除重叠掩模44的整个第二半导体材料层46部分。掩模44的剩余部分在图5f中被清除，留下PFET沟道34和邻近的NFET沟道36。更新近开发的各种方法描述了在硅上选择性地淀积SiGe。利用这种技术，SiGe层46能够被选择性地淀积在暴露的硅沟道核心40上，并能够经由化学腐蚀清除任何残留物。在第一半导体材料层38是硅，且第二半导体材料层46是SixGe1-x的情况下，由SixGe1-x化合物组成的沟道外壳由于下方硅层18较小的天然晶格结构而处于压应力下。
图6示出了一种变通的方法。在图6a中，处置晶片48包括前面所述的埋置氧化物层22以及诸如硅的第一半导体材料的上方层38。图6b示出了使用掩蔽和腐蚀来确定邻接于第一半导体材料层38的剩余部分38a的一个或多个沟槽47。考虑到处置晶片48的总体膨胀，沟槽47和/或第一半导体材料层38的剩余部分38a可以相连或不相连。与图6a-6b所述工艺同时或分隔开一定时间，在图6c中将诸如应变的或驰豫的SiGe之类的第二半导体材料层46层叠在分立的载体晶片50上。然后在图6c中，对具有上方层46的载体晶片50进行离子注入。如本技术领域所知，诸如氢或硼离子的离子52的注入使上层46能够在通常低于大约600℃的温度下被退火并分隔于载体晶片50，同时还提供了无位错的高质量的SiGe。还能够达到SiGe层46的几乎完全(大于或等于95％)应变驰豫。上述工艺在本技术领域中被提出称为“智能切割”技术，并在此处列为参考的论文Lijuan Huang et al，ELECTRON AND HOLE MOBILITY ENHANCEMANT INSTRAINED SOI BY WAFER BONDING，IEEE Transactions onElectron Devices，vol.49，no.9，September 2002，pp.1566-1571中更确切地进行了描述。在图6d中，掩蔽和腐蚀被用来从第二半导体材料层46确定一个或多个小岛49。载体晶片50上小岛49的形状互补于处置晶片48上的沟槽47的形状。薄的氧化物层51优选被设置在至少小岛49上，以便于稍后键合到处置晶片48。一旦形成了小岛49，就可以根据诸如侧壁图象转移之类的熟知的FinFET加工技术来进一步加工。
图6e示出了与图6b的结构结合在一起的图6d结构。在图6e中，载体晶片50被倒置在处置晶片48上。小岛49与沟槽47被彼此准确对准，优选精确到0.25微米以内。智能切割技术的上述退火工艺被用来从载体晶片50移去小岛49。小岛49从而位于沟槽47内，并被薄氧化物层51键合到处置晶片48。优选移去载体晶片50，以便在高温退火和抛光之后重新用作处置晶片。在某些实施方案中，通过上层46的垂直腐蚀以及由此垂直腐蚀限定的离子注入，被用来将一个以上的层(一种以上的半导体材料)组合在小岛49中。如上所述可以安置这种小岛49来配合处置晶片48上的凹陷沟槽47，或可以在处置晶片48上的硅或其它半导体材料的抬高的表面上淀积这种小岛49。如下面更充分地描述的那样，这些实施方案导致二层以上的异质结。
图6f示出了小岛49和剩余部分38a的暴露表面的整平，其中，这些表面与处置晶片48相反。整平和抛光被用来得到基本上均匀的高度。
图6g示出了一个步骤，其中，小岛49和剩余部分38a都被掩蔽和腐蚀即被加工，以便确定一个或多个PFET沟道核心53，优选还确定一个或多个NFET沟道核心55。虽然如此处所述优选同时制作PFET和NFET，但本发明并不要求如此。如图6h所示，不同于第一半导体材料的半导体材料外延层被生长或设置在PFET沟道核心53上，以便形成沟道外壳32，产生应变硅或其它异质层。
依赖于生成的沟道16的所需性质，沟道外壳32的材料可以是应变的或非应变的。沿沟道核心24的相反侧壁表面28或30和底部表面27/顶部表面26所确定的线而出现最大的晶格不连续性。
PFET沟道34或NFET沟道36优选特征在于约为100-150埃的宽度和约为500-600埃的高度。这些尺寸可以按比例改变。应变晶格优选沿PFET沟道34或NFET沟道36的侧壁28和30以及顶部表面26二者设置。
静态随机存取存储器(SRAM)中的FET 10是其中能够利用沿应变侧壁的载流子通道的一种具体应用。SRAM是一种存储器，它不像动态RAM(DRAM)那样需要刷新，故SRAM通常快速得多(典型地说，SRAM约为10ns，而DRAM约为60ns)且更可靠。此外，由于SRAM在各个存取之间不需要暂停，故其周期(存储器芯片能够做到的二个紧挨存取的快速程度的一种度量)比DRAM的短得多。SRAM的设计通常将FET假定为几种固定的尺寸(量子化)。但沟道16的宽度对于SRAM的稳定性是关键的，从而在尺寸与稳定性之间有一折中。为了调制沟道的高度，以便能够得到仍然确保SRAM稳定性的更小的FET 10，可以采用根据本发明的使用鳍的FET 10，而不选择沿x-y平面(图3的平面)的量子化沟道宽度可能比所需更大的FET。在制作过程中，初始硅至少可以与估计的最高的鳍一样高。单元内某些器件的选择性掩蔽和腐蚀对鳍的高度进行裁剪，以便达到所希望的SRAM稳定性。优选采用慢腐蚀来确保均匀性和鳍高度的精细控制。此外，可以利用多个鳍，优选按并列关系，来调整有效沟道宽度。
图7是一系列方框图，示出了制作PFET过程中的各个工艺步骤。图7示出了安放于诸如SiGe之类的第一半导体材料与诸如Si之类的第二半导体材料之间的浅沟槽隔离(STI)。在图7a中，衬底20支持着上面有诸如硅之类的第一半导体材料层38的埋置氧化物层(BOX)22。如前面所述和本技术领域所知那样，此衬底/BOX/上层的组合70，可以是SIMOX晶片、键合晶片、或CZ晶片。在图7b中，形成了沟槽58，并如本技术领域所知，用氧化物或诸如TEOS之类的其它绝缘体填充此沟槽58。要指出的是，在几个步骤中来执行图7b所表示的沟槽形成和填充，且沟槽58将第一半导体材料层38分成第一区域62和PFET区域64。作为变通，可以腐蚀沟槽58而不填充，也不偏离本发明的优点。在图7c中，掩模层44被选择性地设置在沟槽58和第一半导体材料区域62上。在图7d中，PFET区域64被回腐蚀成薄层60，优选厚度约为10nm。在图7e中，在清除掩模44之前或之后，第二半导体材料层46被设置在薄层60上。如图7e所示，薄层60包括水平表面67和基本上垂直的表面68。
第二半导体材料46优选为中等浓度的SiGe。当层46的厚度约为10-30nm时，10-20％的Ge浓度对于热稳定的鳍是优选的。已经发现，更厚的SiGe层46和/或更高的Ge浓度将是亚稳的，并可能需要进一步热处理，但不是退火。本发明的任何一个实施方案优选包括栅介质或栅氧化物的外包层。如图3所示，根据本发明的沟道16可以是FinFET 10的一部分，且FinFET 10优选可以是集成电路100的一部分。如图4所示，沟道16可以包括具有基本上直立的侧壁28和30、顶部表面26、以及底部表面27的沟道核心，或如图7e所示可以被形成为仅仅确定水平表面67和基本上垂直的表面68。作为进一步的变通，如图7f所示，沟道16可以具有从衬底22延伸并在尖锐峰或圆峰71处连结的二个侧壁表面74，以便确定一个与诸如薄层60的剖面之类的此处所示的矩形剖面相反的基本上三角形的剖面75。预计利用顶部上与栅氧化物相接触的应变硅，确定非正交剖面的沟道可能被优化。沟道外壳32可以接触沟道核心24的表面26、27、28、30中的任何二个或所有不接触衬底20的表面26、28、30。与现有技术FinFET相比，在上述任何一个实施方案中，承载电荷(电子或空穴)的应变晶格结构的更宽大的表面被更好地暴露于栅18，使栅18的控制能够更强，且电流输运能够更为有效。
图8说明了根据此处论述的FinFET结构的各种其它的实施方案。在图8所示的各种实施方案中，各结构包括具有上方应变硅层的驰豫的Si-Ge层。这种组合提供了改进的电子-空穴迁移率。
图8A-B所示的沟道16由沟道核心24组成，且上方有图4所示的沟道外壳32。如图8所示，衬底20包括埋置的氧化物层22以及硅层21。图8所示的各个结构包括源12、漏14、以及沟道16。还示出了了设置在沟道16与各个栅之间的介质层33。由于沟道16在图8C-E所示的结构内部，因而不可见，仅仅在图8A-B和8F中示出了沟道16。尽管如此，图8A-8F的各个实施方案可以包括如前面所述的沟道核心24和沟道外壳32。
在图8A中，示出了一种单栅FinFET 90。在此实施方案中，沟道16包括驰豫的Si-Ge层和应变硅层。薄的氧化物层33被设置在沟道16与单栅95之间。图8B表示FinFET的一种双栅实施方案91。除了图8A所示的单栅95之外，表示了一个第二栅96。在此实施方案中，第二栅96被埋置在埋置氧化物层22中的沟槽内。图8C示出了一种三栅FinFET 92，其中，三重栅97被形成在设置于沟道16(图8A-B所示)上的薄的氧化物层33上。图8D示出了一种四栅FinFET93，其中，四重栅98有效地环绕着沟道16。在图8D中，部分四重栅98被潜入埋置的氧化物层22中。在图8E中，示出了一种具有Pi栅99的FinFET94。Pi栅99向下延伸，并至少部分地进入到埋置的氧化物层22中。
图8F是双栅FinFET 87的另一实施方案，确定了第一栅88和第二栅89。可以例如借助于对图8C的FinFET进行抛光，直至清除沟道16上方的图8C的三重栅97部分，留下图8F的双栅88和89，来形成图8F的FinFET。沟道优选包括应变的硅锗。图8F栅安排的一个优点在于各个栅88和89可以被独立地控制，致使例如第一栅88是典型的FinFET栅，而第二栅89可以施加可变电压。以这种方式，当源12与漏14之间的电流在开通与关断之间转换时，第二栅89是一个控制耗尽区的背栅。这种第二栅89利用可变电压更好地控制了第一栅88的泄漏和性能；致使仅仅施加控制泄漏电流所必须的最小电压。
在四重栅FinFET 93和Pi栅FinFET 94上淀积应变硅层，其中，FinFET 93和94是PFET(不是NFET)，改善了PFET中的迁移率，同时保留了PFET和NFET的有益方面。还要指出的是，沿[110]方向淀积应变硅层也改善迁移率。[110]方向与结晶轴成45度角。
图9示出了6晶体管SRAM单元的一个实施方案。为了SRAMFinFET量子化，优选在6晶体管常规SRAM中最小的器件(例如NFET通过门77(Pg)和上拉PFET 76(PL)的尺寸较小)上进行PFET量子化。这样，鳍高度的量子化能够基于各个器件，即将通过门NFET和上拉PFET定在一个量子高度，并将较大的NFET 78(Cc)定在另一个量子高度。或者，可以采用用于图8A-F所示实施方案的多个NFET和PFET器件中的较小的鳍高度。这一量子化将有助于形成耐用而稳定的单元。
虽然在这些优选实施方案中进行了描述，但本技术领域的熟练人员能够对上述各个实施方案做出各种修正和改变，且所有这些修正和改变仍然在本发明和所附权利要求的范围内。此处的各个例子被认为是示例性的而不是本发明论述的全部。

Claims (5)

1.一种用来电连接场效应晶体管的源和漏的沟道，包括：
耦合到衬底并确定与衬底分隔开的顶部表面以及衬底与顶部表面之间相反的侧壁表面的沟道核心，其中，沟道核心包括确定第一晶格结构的第一半导体材料，并且至少一个侧壁表面确定高度hc，而所述顶部表面确定宽度wc，且hc≥3wc；
与所述相反的侧壁表面和所述顶部表面相接触的沟道外壳，其中，沟道外壳包括确定不同于第一晶格结构的第二晶格结构的第二半导体材料；以及
设置在与沟道核心面对的沟道外壳表面周围的栅氧化物。
2.权利要求1的沟道，还包括通过栅氧化物耦合到沟道外壳所确定的至少二个表面的栅。
3.权利要求1的沟道，其中，沟道是场效应晶体管的组成部分，而场效应晶体管是静态随机存取存储器的组成部分，且至少一个侧壁表面确定高度hc，此高度hc被选择来提高静态随机存取存储器稳定性。
4.权利要求1的沟道，其中，第二半导体材料覆盖二个侧壁表面和顶部表面。
5.权利要求1的沟道，其中，第一和第二半导体材料之一包括硅和锗。
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