CN100466229C - 多高度鳍片场效应晶体管及其制造方法 - Google Patents

多高度鳍片场效应晶体管及其制造方法 Download PDF

Info

Publication number
CN100466229C
CN100466229C CNB2004800120281A CN200480012028A CN100466229C CN 100466229 C CN100466229 C CN 100466229C CN B2004800120281 A CNB2004800120281 A CN B2004800120281A CN 200480012028 A CN200480012028 A CN 200480012028A CN 100466229 C CN100466229 C CN 100466229C
Authority
CN
China
Prior art keywords
fin
height
finfet device
grid conductor
silicon layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2004800120281A
Other languages
English (en)
Other versions
CN1784782A (zh
Inventor
B·A·雷尼
E·J·诺瓦克
I·阿勒
J·凯纳特
T·卢德维格
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN1784782A publication Critical patent/CN1784782A/zh
Application granted granted Critical
Publication of CN100466229C publication Critical patent/CN100466229C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes

Abstract

本发明提供了一种FinFET器件，其具有第一鳍片和第二鳍片。每个鳍片具有沟道区域和从沟道区域延伸的源极和漏极区域。所述鳍片具有不同的高度。本发明具有位于邻近所述鳍片的栅极导体。所述栅极导体垂直于所述鳍片延伸并横跨每个第一鳍片和第二鳍片的沟道区域。所述鳍片相互平行。第一鳍片的高度与第二鳍片的高度的比率包括比率1比2/3。所述比率用于调节晶体管的性能并确定晶体管的总沟道宽度。

Description

多高度鳍片场效应晶体管及其制造方法
技术领域
本发明涉及场效应晶体管，更具体地说，涉及鳍片场效应晶体管和涉及具有不同高度鳍片的这种结构。
背景技术
自从1960年集成电路(“IC”)首次产生和制造，在IC衬底上形成的器件的数量和密度已惊人地增长。事实上，一般认为在一个芯片上具有多于100,000个器件的超大规模集成(“VLSI”)器件是陈旧的技术。在当今的市场上，在一个芯片上具有数亿个器件的IC的制造是标准的技术。在每个芯片上具有数十亿个器件的IC发展目前正在进行。因此，IC制造的当前描述是甚大规模集成(“ULSI”)。
随着形成在IC衬底上的器件数量的部分增加以及同时器件密度的增长，器件的尺寸显著地降低。尤其，栅极厚度和源极与漏极部分的沟道间距的尺寸持续地降低，以使得满足当前源极、漏极和栅极的微米和纳米间距的需要。尽管器件在尺寸上已经稳定降低，器件的性能必须保持或提高。除了器件的性能特性、性能可靠性和耐用性，制造可靠性和成本也始终是决定性的问题。
由器件的小型化引起几个问题包括短沟道效应、穿通现象和漏电流。这些问题影响器件的性能和制造工艺。短沟道效应对器件性能的影响从器件阈值电压的降低和亚阈值电流的增加可以看出。
更具体地，随着沟道长度越来越小，源极和漏极耗尽区变得越来越相互接近。耗尽区基本上占据源极和漏极之间的整个沟道区域。由源极和漏极耗尽区产生的沟道区域的该有效占据的结果是，沟道被部分耗尽，并且减少了改变源极和漏极电流所必需的栅极电荷。
用于降低或消除短沟道效应的一种方法是降低邻近源极和漏极的栅极氧化物的厚度。薄的栅极氧化物不仅会降低短沟道效应，它们也允许较高的驱动电流。一个结果是加快器件。然而，如所希望的，关于制造薄的氧化物存在显著的问题，包括制造的重复性和均匀性以及在制造工艺期间氧化物生长速度的控制。
为了解决短沟道效应以及关于ULSI的其他问题，对器件已经作出改进，并持续进行对器件的改进。在Muller等人(以下称为“Muller”，再次通过参考将其并入文本)的美国专利6,252,284中描述了这种尝试中的一种，其公开了一种场效应晶体管(FET)，包括具有鳍片形状的沟道区域，且将其称作鳍片FET器件。这在图1中示出。在鳍状FET型结构中，沟道24和源极及漏极区域4形成为从衬底5延伸的垂直硅鳍片结构。垂直栅极结构21与鳍片结构的沟道区域24交叉。尽管在图1中未示出，各种绝缘层将沟道区域24与栅极21电隔离。图1也说明了氧化物层20和形成于鳍片结构4、24和栅极结构21上的绝缘侧壁隔离物12、23。鳍片结构4的端部接收使得鳍片结构的这些区域导电的源极和漏极掺杂注入。掺杂鳍片结构的沟道区域24以使得硅包括半导体，其只有当在栅极21中存在足够的电压/电流时才导电。
然而，形成常规的鳍片FET器件以使得所有的鳍片FET晶体管在给出的芯片上具有相同的鳍片高度。以下描述的本发明提供了一种方法以在单个的芯片上制造不同的鳍片高度，和一种在不同鳍片的不同高度之间选择适当的比率的方法。
发明内容
本发明提供了一种FinFET器件，其具有第一鳍片和第二鳍片。每个鳍片具有沟道区域和从沟道区域延伸的源极和漏极区域。所述鳍片具有不同的高度。本发明具有位于邻近所述鳍片的栅极导体。所述栅极导体垂直于所述鳍片延伸并横跨每个第一鳍片和第二鳍片的沟道区域。所述鳍片相互平行。第一鳍片的高度与第二鳍片的高度的比率包括比率1比2/3。所述比率用于调节晶体管的性能并确定晶体管的总沟道宽度。
本发明还提供了具有第一鳍片FET晶体管和第二鳍片FET晶体管的集成电路，该第一鳍片FET晶体管具有第一鳍片，第二鳍片FET晶体管具有第二鳍片。每个鳍片包括沟道区域和从沟道区域延伸的源极和漏极区域。该鳍片具有不同的高度。本发明还具有多个FinFET器件，每个具有至少一个鳍片。每个鳍片包括沟道区域和从沟道区域延伸的源极和漏极区域。在集成电路中的至少两个鳍片具有不同的高度。
因此，本发明提供了一种制造FinFET器件的方法。首先，本发明在结构上形成有源硅层。接下来，本发明构图在有源硅层上的掩模。然后本方法进行热氧化以降低未被掩模保护的有源硅层区域的高度。本方法移除该掩模，并将有源硅层构图为鳍片。当与从有源硅层的其它区域产生的鳍片相比较时，从缩短区域产生的鳍片具有较小的高度。
该方法首先始于SOI晶片，在有源硅层上形成氧化物，然后在氧化物上形成第一掩模层。然后，构图该晶片以暴露出有源硅的区域以热氧化不被掩模层保护的有源硅。控制该热氧化处理以降低非掩模区域的高度至有源硅层高度的2/3。该热氧化处理用于调节FinFET器件的性能，并确定FinFET器件的沟道宽度。在形成氧化物之后，移除第一掩模层，并构图第二掩模层。然后，该方法蚀刻未被第二掩膜保护的氧化物，然后剥离掩模。该处理继续进行相对于暴露氧化物具有选择性地蚀刻有源硅以形成鳍片。然后，该方法构图在鳍片上的栅极导体以使得栅极导体横跨鳍片的沟道区域。最后的处理是本领域中公知的，且在此不再讨论。
本发明还提供了一种制造具有FinFET器件的集成电路的方法。首先，该方法在结构上形成有源硅层。然后，该方法构图在有源硅层上的掩模。然后该方法进行热氧化以降低未被掩模保护的有源硅层的缩短区域的高度。该方法移除掩模并将有源硅层构图为鳍片。当与从有源硅层的其它区域产生的鳍片相比较时，从缩短区域产生的鳍片具有较小的高度。
因此，如上所示，本发明允许根据电路设计者的需要、通过使用具有不同高度的多个鳍片来调整FinFET器件。而且，本发明建立了1比2/3的最优高度比率以允许高沟道宽度量化(granularity)，而不牺牲产量以及不扰乱常规晶体管制造工艺。
附图说明
图1是常规FinFET结构的示意图；
图2A是在集成电路芯片内部的截面中的多鳍片FinFET器件的示意图；
图2B是从顶面透视的图2A中示出的器件的示意图；
图3是说明在制造FinFET器件的发明工艺中的步骤的示意图；
图4是说明在制造FinFET器件的发明工艺中的步骤的示意图；
图5是说明在制造FinFET器件的发明工艺中的步骤的示意图；
图6是说明在制造FinFET器件的发明工艺中的步骤的示意图；
图7是说明在制造FinFET器件的发明工艺中的步骤的示意图；
图8是说明在制造FinFET器件的发明工艺中的步骤的示意图；
图9是说明在制造FinFET器件的发明工艺中的步骤的示意图；以及
图10是说明本发明优选方法的流程图。
具体实施方式
一组模拟类电路对晶体管沟道宽度非常敏感，且尤其对在器件中含有的不同FET的沟道宽度的比率非常敏感，其中该一组模拟类电路在逻辑上例如读出放大器、锁存器和SRAM单元。因此，在芯片内部的不同电路的性能可以通过改变在器件内部的一个或多个FET的沟道宽度来调整。这允许设计者在芯片上所需要的地方改变不同逻辑电路的性能。
对于FinFET结构，沟道宽度正比于鳍片高度，这是因为，在FinFET器件中沟道宽度是垂直的。由于鳍片的两侧都暴露于但绝缘于栅极，因此沟道宽度实际上是由鳍片高度(乘以鳍片长度)产生的区域的两倍。因此，通过增加或降低鳍片高度(对于给定的鳍片长度)，沟道宽度(暴露于但绝缘于栅极的沟道表面区域)也相应地增加或降低。本发明提供一种方法以制造具有不同鳍片高度(沟道宽度)的FinFET，以允许根据设计者的需要调节FinFET器件的性能。
图2A是说明形成于部分集成电路芯片内的多鳍片FinFET晶体管的侧面截面图的示意图。图2B是从顶面透视的其结构的示意图。该示意图说明衬底30、氧化物31、多个鳍片32、绝缘材料60和形成于鳍片32和绝缘体60上的栅极导体90。如关于在图1中的透视图可以更清楚地看出，在图2A中示出的鳍片32延伸至页面中并延伸出页面，且在其端部包括源极和漏极区域4。如在图2B中所示，栅极90垂直于鳍片32延伸并横跨每个鳍片32的沟道区域24。
如在图2A中所示，本发明可对每个FinFET使用多个鳍片。如在图2B中所示，不同鳍片的所有源极和漏极电连接至外部引线25，以使得当选通(gating)源极和漏极之间的导电性时，所有鳍片32共同作用。通过使用多个鳍片，电路设计者可以增加或降低暴露于但绝缘于栅极的沟道区域24。因此，对于具有相同长度和高度的鳍片来讲，当与单个鳍片相比时，两个鳍片可以使有效沟道宽度加倍，三个鳍片可以使有效沟道宽度增加三倍，等等。而且，通过提供具有在单个的晶体管中使用不同高度鳍片能力的设计，本发明允许沟道表面区域变化的较好量化，由此允许更好地调整芯片内部不同电路之间的分辨率。
图3-9通过示出发明结构的各种制造步骤说明本发明所利用的一种方法。更具体地，图3说明具有在掩埋氧化层31顶部上的有源(例如，半导电)硅层32的SOI晶片的使用。标号33表示在一实施例中的二氧化硅。在另一个实施例中，标号33表示具有上覆多晶硅层的二氧化硅。标号34表示形成于层33上的氮化硅层。
在图4中，在氮化硅层34上形成并构图光致抗蚀剂40。然后，蚀刻该结构以移除该结构的暴露部分41直至有源硅层32。然后，如在图5中所示，该结构经历高温氧化处理。该氧化处理消耗了经由抗蚀剂中的开口41暴露的部分有源硅32。然后移除该光致抗蚀剂40。如在图5中所示，这降低了在选择的区域41中的有源硅32的高度。当通过继续上面关于图4讨论的蚀刻处理来降低有源硅区32的高度时，该氧化处理在暴露区域41的高度降低上产生更高级别的控制。
在图6中，使用选择性移除处理剥离氮化物34。另外，如果层33包括多晶硅部分，多晶硅也可以在该步骤中选择性地移除。然后，在将形成鳍片的位置处施加并构图掩膜材料60。在图7中，在不影响下层硅32的选择性蚀刻处理中蚀刻氧化物。然后，如图8中所示，剥离掩膜材料60，且相对于氧化物31选择性蚀刻未被氧化物33保护的硅32的区域以形成鳍片32。在氧化处理(上面关于图5所讨论的)中降低了硅32的高度的区域41中形成鳍片80，而鳍片81形成于有源硅32的高度没有降低的区域中。因此，与鳍片81相比较，鳍片80具有降低了的高度。在图9中，淀积并构图导电栅极材料90。另外，如在FinFET技术领域中已知的，进行附加的处理以完成该晶体管。例如，掺杂鳍片延伸超出栅极材料4的区域以产生源极和漏极区域；形成绝缘层，形成至栅极、源极和漏极的接触，等等。在该例子中，形成三个晶体管91-93。
尽管在图2B中示出了垂直于含有沟道区域24的鳍片的构图的栅极导体90，有利的是使栅极导体以90度以外的角度横跨鳍片以在特定的晶面上形成沟道。尤其，允许栅极以67.5度的角度横跨鳍片可以允许穿过{110}和{100}面，以在硅中分别产生空穴和电子的最高迁移率。
图10是示出本发明的实施例的流程图。在标号100中，本发明使用但不限于SOI晶片作为起始点。然后在标号102中，本发明在有源硅层上形成氧化层。然后，在标号104中，本发明构图在氧化层上的掩模或掩模层。在标号106中，本发明进行热氧化以降低未被掩膜保护的有源硅层区域的高度。在标号108中，本发明移除掩模或掩模层。然后，在标号110中，本发明构图在氧化物和有源硅层上的第二掩模。在标号112中，本发明将有源硅层构图为鳍片。然后本发明在标号114中的鳍片的沟道区域上形成栅极氧化物。在标号116中，本发明构图在鳍片上的栅极导体以使得栅极导体横跨鳍片的沟道区域。最后，在标号118中，本发明掺杂未被栅极导体覆盖的部分鳍片以在鳍片中形成源极和漏极区域。
如上所示，本发明在给定芯片内的不同FinFET器件的鳍片高度上提供独立的控制，以允许调整沟道宽度来实现某一性能目标。另外，本发明提供以下的关于选择不同的鳍片高度的方法。
以下描述的内容包括单个高温氧化处理以降低将要构图为鳍片的有源硅的选择部分的高度。可使用不同掩模重复该处理很多不同的次数，以产生三个或更多个不同的鳍片高度(如与上面讨论的两个鳍片高度不同)。然而，本发明限制了通过利用下面讨论的鳍片高度比率进行大量高温氧化处理的需要。
该方法限制了鳍片高度(和相关沟道宽度)至基础鳍片高度的倍数(量)，以简化处理并允许设计者最宽范围的沟道宽度选择，同时保持合理的制造处理步骤。由于光刻形成该鳍片(如上面讨论的)，因此该鳍片可以以不大于接近光刻规格的频率相间隔(例如，对于70nm技术以70nm相间隔)。由于必须使用较少的鳍片以实现希望的沟道宽度，因此较高的鳍片可给出每单元区域较高的电流密度；然而，这导致了较大沟道宽度步骤(较粗糙的量化)。较小的鳍片允许沟道宽度的较好量化；然而，这会消耗过多的芯片面积。
为了围绕这些要点工作，本发明建立了较小鳍片具有较高鳍片高度的2/3的高度的标准。通过试验，本发明者已经确定该比率产生最优的设计解决方案的结果。该解决方案允许利用单独的高温氧化处理(由此保持高产量)。而且，通过在相互的1/3内形成鳍片的高度，不需要更改在晶体管中形成剩余结构的处理。相反，如果将某些鳍片制作得明显小于其它，对于明显较短的鳍片来讲，则将必须利用特定的处理以形成接触、源极、漏极、氧化物，等等。
在图9中示出本发明1比2/3比率的使用(例如，1:0.667比率)。在晶体管91中，沟道宽度等于1(如上所述，其事实上是鳍片高度的两倍)。图9通过邻近晶体管91的等式W＝(1)×2h表示出这个。晶体管92具有如通过等式W＝(4/3)×2h表示的4/3的沟道宽度。这通过使用两个高度鳍片实现。作为另一个例子，晶体管93具有通过组合2/3高度鳍片和全高度鳍片形成的5/3的沟道宽度(如通过等式W＝(5/3)×2h所表示)。因此，通过以多重组合使用全高度和2/3高度鳍片，实际上可以通过本发明实现任何沟道宽度而基本上不改变标准晶体管制造工艺或降低产量。
因此，如上所示，本发明根据电路设计者的需要、通过使用可具有不同高度的多重鳍片可允许调节鳍片FET器件。而且，本发明建立1比2/3的最优高度比率以允许高的沟道宽度量化，而不牺牲产量以及不扰乱常规晶体管制造工艺。
通过本发明能实现的沟道宽度的较好量化允许这些电路严格依赖于晶体管内部的相对驱动强度或性能工作，以较其它可能方法占用较少的物理区域。而且，在这些电路中可以实现较窄的总沟道宽度，由此当与常规结构相比较时，导致获得的电路的较低功率消耗。
虽然已经依照优选实施例描述了本发明，但是本领域技术人员将认识到，在所附权利要求的精神和范围内通过修改可以实施本发明。
工业适用性
本发明用于半导体器件领域，具体地，用于包括场效应晶体管的器件。

Claims (22)

1.一种FinFET器件，包括:
第一鳍片(80)和第二鳍片(81)，每个鳍片包括沟道区域和从所述沟道区域延伸的源极和漏极区域，
其中所述第一鳍片(80)和所述第二鳍片(81)具有不同的高度。
2.根据权利要求1的FinFET器件，还包括位于邻近所述第一鳍片和所述第二鳍片的栅极导体(90)，其中所述栅极导体相对于所述第一鳍片以67.5度的角度延伸。
3.根据权利要求1的FinFET器件，还包括位于邻近所述第一鳍片和所述第二鳍片的栅极导体(90)，其中所述栅极导体垂直于所述第一鳍片和所述第二鳍片延伸。
4.根据权利要求3的FinFET器件，其中所述栅极导体(90)横跨每个所述第一鳍片和第二鳍片的所述沟道区域。
5.根据权利要求1的FinFET器件，其中所述第一鳍片(80)和所述第二鳍片(81)相互平行。
6.根据权利要求1的FinFET器件，其中所述第一鳍片(80)的高度与所述第二鳍片(81)的高度的比率为1比2/3。
7.根据权利要求6的FinFET器件，其中所述比率用于调节所述FinFET器件的性能。
8.根据权利要求6的FinFET器件，其中所述比率确定所述FinFET器件的总沟道宽度。
9.一种集成电路，包括根据权利要求1的FinFET器件。
10.根据权利要求9的集成电路，其中第一栅极导体位于邻近所述第一鳍片(80)，且所述第一栅极导体垂直于所述第一鳍片(80)延伸，以及
其中第二栅极导体位于邻近所述第二鳍片(80)，且所述第二栅极导体垂直于所述第二鳍片(81)延伸。
11.根据权利要求10的集成电路，其中所述第一栅极导体横跨所述第一鳍片(80)的所述沟道区域，且其中所述第二栅极导体横跨所述第二鳍片(81)的所述沟道区域。
12.根据权利要求9的集成电路，其中所述第一鳍片(80)的高度与所述第二鳍片(81)的高度的比率为1比2/3。
13.根据权利要求12的集成电路，其中所述比率用于调节所述电路的性能。
14.根据权利要求12的集成电路，其中所述比率确定所述第一鳍片(80)和所述第二鳍片(81)的沟道宽度。
15.一种集成电路，包括多个根据权利要求1的FinFET器件。
16.一种制造根据权利要求1的FinFET器件的方法，该方法包括以下步骤:
在结构上形成有源硅层(102)；
构图在所述有源硅层上的掩模(104)；
进行热氧化以降低未被所述掩模保护的所述有源硅层区域的高度(106)；
移除所述掩模(108)；以及
将所述有源硅层构图为鳍片，其中当与从所述有源硅层的其它区域产生的鳍片相比较时，从所述高度被降低的有源硅层区域产生的鳍片具有较小的高度(112)。
17.根据权利要求16的方法，还包括通过在硅衬底上生长底部氧化物来形成所述结构(100)。
18.根据权利要求16的方法，其中所述有源硅层的所述构图为鳍片的步骤(112)包括以下步骤:
构图在所述有源硅层上的第二掩模；以及
将所述有源硅层的区域蚀刻为所述鳍片。
19.根据权利要求16的方法，还包括构图在所述鳍片上的栅极导体，以使所述栅极导体横跨所述鳍片的沟道区域(116)。
20.根据权利要求16的方法，其中控制所述热氧化处理(106)以将所述缩短区域的所述高度降低到所述有源硅层高度的2/3。
21.根据权利要求16的方法，其中所述热氧化处理(106)用于调节所述FinFET器件的性能。
22.根据权利要求16的方法，其中所述热氧化处理(106)确定所述FinFET器件的总沟道宽度。
CNB2004800120281A 2003-05-05 2004-01-30 多高度鳍片场效应晶体管及其制造方法 Expired - Fee Related CN100466229C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/249,738 2003-05-05
US10/249,738 US6909147B2 (en) 2003-05-05 2003-05-05 Multi-height FinFETS

Publications (2)

Publication Number Publication Date
CN1784782A CN1784782A (zh) 2006-06-07
CN100466229C true CN100466229C (zh) 2009-03-04

Family

ID=33415537

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004800120281A Expired - Fee Related CN100466229C (zh) 2003-05-05 2004-01-30 多高度鳍片场效应晶体管及其制造方法

Country Status (8)

Country Link
US (1) US6909147B2 (zh)
EP (1) EP1620891B1 (zh)
KR (1) KR100690559B1 (zh)
CN (1) CN100466229C (zh)
AT (1) ATE403937T1 (zh)
DE (1) DE602004015592D1 (zh)
TW (1) TWI289354B (zh)
WO (1) WO2004100290A2 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9418903B2 (en) 2014-05-21 2016-08-16 Globalfoundries Inc. Structure and method for effective device width adjustment in finFET devices using gate workfunction shift

Families Citing this family (105)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005005621A (ja) * 2003-06-13 2005-01-06 Toyota Industries Corp Ｄｃアンプ及びその半導体集積回路
US6992354B2 (en) * 2003-06-25 2006-01-31 International Business Machines Corporation FinFET having suppressed parasitic device characteristics
US6894326B2 (en) * 2003-06-25 2005-05-17 International Business Machines Corporation High-density finFET integration scheme
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US6909151B2 (en) 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US7095065B2 (en) * 2003-08-05 2006-08-22 Advanced Micro Devices, Inc. Varying carrier mobility in semiconductor devices to achieve overall design goals
JP2005086024A (ja) * 2003-09-09 2005-03-31 Toshiba Corp 半導体装置及びその製造方法
US6970373B2 (en) * 2003-10-02 2005-11-29 Intel Corporation Method and apparatus for improving stability of a 6T CMOS SRAM cell
US7701018B2 (en) * 2004-03-19 2010-04-20 Nec Corporation Semiconductor device and method for manufacturing same
KR100576361B1 (ko) * 2004-03-23 2006-05-03 삼성전자주식회사 3차원 시모스 전계효과 트랜지스터 및 그것을 제조하는 방법
DE102004020593A1 (de) * 2004-04-27 2005-11-24 Infineon Technologies Ag Fin-Feldeffekttransistor-Anordnung und Verfahren zum Herstellen einer Fin-Feldeffektransistor-Anordnung
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7332439B2 (en) 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7183142B2 (en) * 2005-01-13 2007-02-27 International Business Machines Corporation FinFETs with long gate length at high density
US7094650B2 (en) * 2005-01-20 2006-08-22 Infineon Technologies Ag Gate electrode for FinFET device
US7470951B2 (en) * 2005-01-31 2008-12-30 Freescale Semiconductor, Inc. Hybrid-FET and its application as SRAM
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
JP2006269975A (ja) * 2005-03-25 2006-10-05 Toshiba Corp 半導体装置及びその製造方法
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7402875B2 (en) 2005-08-17 2008-07-22 Intel Corporation Lateral undercut of metal gate in SOI device
US7479421B2 (en) 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US20070090416A1 (en) 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
JP2007103455A (ja) * 2005-09-30 2007-04-19 Toshiba Corp フィン構造の半導体装置及びその製造方法
US7452768B2 (en) 2005-10-25 2008-11-18 Freescale Semiconductor, Inc. Multiple device types including an inverted-T channel transistor and method therefor
US8513066B2 (en) * 2005-10-25 2013-08-20 Freescale Semiconductor, Inc. Method of making an inverted-T channel transistor
US20070117311A1 (en) * 2005-11-23 2007-05-24 Advanced Technology Development Facility, Inc. Three-dimensional single transistor semiconductor memory device and methods for making same
US7709303B2 (en) * 2006-01-10 2010-05-04 Freescale Semiconductor, Inc. Process for forming an electronic device including a fin-type structure
US7754560B2 (en) * 2006-01-10 2010-07-13 Freescale Semiconductor, Inc. Integrated circuit using FinFETs and having a static random access memory (SRAM)
US7723805B2 (en) * 2006-01-10 2010-05-25 Freescale Semiconductor, Inc. Electronic device including a fin-type transistor structure and a process for forming the electronic device
US7323373B2 (en) * 2006-01-25 2008-01-29 Freescale Semiconductor, Inc. Method of forming a semiconductor device with decreased undercutting of semiconductor material
US7419866B2 (en) * 2006-03-15 2008-09-02 Freescale Semiconductor, Inc. Process of forming an electronic device including a semiconductor island over an insulating layer
US7456055B2 (en) 2006-03-15 2008-11-25 Freescale Semiconductor, Inc. Process for forming an electronic device including semiconductor fins
US7628932B2 (en) 2006-06-02 2009-12-08 Micron Technology, Inc. Wet etch suitable for creating square cuts in si
US7625776B2 (en) 2006-06-02 2009-12-01 Micron Technology, Inc. Methods of fabricating intermediate semiconductor structures by selectively etching pockets of implanted silicon
US7709341B2 (en) * 2006-06-02 2010-05-04 Micron Technology, Inc. Methods of shaping vertical single crystal silicon walls and resulting structures
US7544994B2 (en) * 2006-11-06 2009-06-09 International Business Machines Corporation Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure
US7655989B2 (en) * 2006-11-30 2010-02-02 International Business Machines Corporation Triple gate and double gate finFETs with different vertical dimension fins
US7709893B2 (en) * 2007-01-31 2010-05-04 Infineon Technologies Ag Circuit layout for different performance and method
US7612405B2 (en) * 2007-03-06 2009-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Fabrication of FinFETs with multiple fin heights
US7560785B2 (en) * 2007-04-27 2009-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having multiple fin heights
CN100527442C (zh) * 2007-06-05 2009-08-12 北京大学 一种双鳍型沟道双栅多功能场效应晶体管及其制备方法
US20090001470A1 (en) * 2007-06-26 2009-01-01 Anderson Brent A Method for forming acute-angle spacer for non-orthogonal finfet and the resulting structure
US7737501B2 (en) * 2007-07-11 2010-06-15 International Business Machines Corporation FinFET SRAM with asymmetric gate and method of manufacture thereof
US7859044B2 (en) * 2007-07-24 2010-12-28 International Business Machines Corporation Partially gated FINFET with gate dielectric on only one sidewall
US20090057780A1 (en) * 2007-08-27 2009-03-05 International Business Machines Corporation Finfet structure including multiple semiconductor fin channel heights
US20090057846A1 (en) * 2007-08-30 2009-03-05 Doyle Brian S Method to fabricate adjacent silicon fins of differing heights
US7791063B2 (en) * 2007-08-30 2010-09-07 Intel Corporation High hole mobility p-channel Ge transistor structure on Si substrate
US7710765B2 (en) * 2007-09-27 2010-05-04 Micron Technology, Inc. Back gated SRAM cell
US7888750B2 (en) * 2008-02-19 2011-02-15 International Business Machines Corporation Multi-fin multi-gate field effect transistor with tailored drive current
US8022478B2 (en) * 2008-02-19 2011-09-20 International Business Machines Corporation Method of forming a multi-fin multi-gate field effect transistor with tailored drive current
US8048723B2 (en) * 2008-12-05 2011-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium FinFETs having dielectric punch-through stoppers
US8106459B2 (en) 2008-05-06 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs having dielectric punch-through stoppers
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US20090321834A1 (en) * 2008-06-30 2009-12-31 Willy Rachmady Substrate fins with different heights
JP5442235B2 (ja) * 2008-11-06 2014-03-12 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
US8263462B2 (en) * 2008-12-31 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric punch-through stoppers for forming FinFETs having dual fin heights
US8293616B2 (en) 2009-02-24 2012-10-23 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of fabrication of semiconductor devices with low capacitance
US7855105B1 (en) * 2009-06-18 2010-12-21 International Business Machines Corporation Planar and non-planar CMOS devices with multiple tuned threshold voltages
US8188546B2 (en) * 2009-08-18 2012-05-29 International Business Machines Corporation Multi-gate non-planar field effect transistor structure and method of forming the structure using a dopant implant process to tune device drive current
US8021949B2 (en) * 2009-12-01 2011-09-20 International Business Machines Corporation Method and structure for forming finFETs with multiple doping regions on a same chip
US20110147848A1 (en) * 2009-12-23 2011-06-23 Kuhn Kelin J Multiple transistor fin heights
US8524545B2 (en) 2010-10-22 2013-09-03 International Business Machines Corporation Simultaneous formation of FinFET and MUGFET
US8524546B2 (en) 2010-10-22 2013-09-03 International Business Machines Corporation Formation of multi-height MUGFET
CN103022038B (zh) * 2011-09-21 2015-06-10 中国科学院微电子研究所 Sram单元及其制作方法
US8497198B2 (en) * 2011-09-23 2013-07-30 United Microelectronics Corp. Semiconductor process
CN103187284B (zh) * 2011-12-29 2015-10-14 中芯国际集成电路制造(上海)有限公司 场效应晶体管的制作方法
US8809178B2 (en) 2012-02-29 2014-08-19 Globalfoundries Inc. Methods of forming bulk FinFET devices with replacement gates so as to reduce punch through leakage currents
KR101823105B1 (ko) 2012-03-19 2018-01-30 삼성전자주식회사 전계 효과 트랜지스터의 형성 방법
US8927432B2 (en) * 2012-06-14 2015-01-06 International Business Machines Corporation Continuously scalable width and height semiconductor fins
US9583398B2 (en) 2012-06-29 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having FinFETS with different fin profiles
US9082873B2 (en) 2012-09-20 2015-07-14 International Business Machines Corporation Method and structure for finFET with finely controlled device width
CN103811340B (zh) * 2012-11-09 2017-07-14 中国科学院微电子研究所 半导体器件及其制造方法
US9123654B2 (en) * 2013-02-15 2015-09-01 International Business Machines Corporation Trilayer SIT process with transfer layer for FINFET patterning
US9159576B2 (en) 2013-03-05 2015-10-13 Qualcomm Incorporated Method of forming finFET having fins of different height
TWI570812B (zh) * 2013-03-06 2017-02-11 聯華電子股份有限公司 形成鰭狀結構的方法
US9331201B2 (en) 2013-05-31 2016-05-03 Globalfoundries Inc. Multi-height FinFETs with coplanar topography background
US9293466B2 (en) 2013-06-19 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded SRAM and methods of forming the same
CN104253046B (zh) * 2013-06-26 2016-12-28 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法
US9093275B2 (en) 2013-10-22 2015-07-28 International Business Machines Corporation Multi-height multi-composition semiconductor fins
US9704880B2 (en) * 2013-11-06 2017-07-11 Taiwan Semiconductor Manufacturing Company Limited Systems and methods for a semiconductor structure having multiple semiconductor-device layers
MY188063A (en) 2013-12-23 2021-11-15 Intel Corp Advanced etching techniques for straight, tall and uniform fins across multiple fin pitch structures
US9190466B2 (en) 2013-12-27 2015-11-17 International Business Machines Corporation Independent gate vertical FinFET structure
US9691763B2 (en) 2013-12-27 2017-06-27 International Business Machines Corporation Multi-gate FinFET semiconductor device with flexible design width
US9318488B2 (en) 2014-01-06 2016-04-19 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device and formation thereof
US20150287743A1 (en) 2014-04-02 2015-10-08 International Business Machines Corporation Multi-height fin field effect transistors
US9887196B2 (en) 2014-04-07 2018-02-06 International Business Machines Corporation FinFET including tunable fin height and tunable fin width ratio
US9793269B2 (en) * 2014-08-07 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
KR102245133B1 (ko) 2014-10-13 2021-04-28 삼성전자 주식회사 이종 게이트 구조의 finFET를 구비한 반도체 소자 및 그 제조방법
KR102352154B1 (ko) * 2015-03-03 2022-01-17 삼성전자주식회사 집적회로 소자
US9515089B1 (en) 2015-05-14 2016-12-06 International Business Machines Corporation Bulk fin formation with vertical fin sidewall profile
WO2017052585A1 (en) * 2015-09-25 2017-03-30 Intel Corporation High-voltage transistor with self-aligned isolation
US9577066B1 (en) 2016-02-26 2017-02-21 Globalfoundries Inc. Methods of forming fins with different fin heights
DE102017125352B4 (de) * 2017-08-30 2020-07-09 Taiwan Semiconductor Manufacturing Co., Ltd. Verfahren zur Bildung von FinFETs
US10541319B2 (en) 2017-08-30 2020-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Fin structures having varied fin heights for semiconductor device
US10068902B1 (en) 2017-09-26 2018-09-04 Globalfoundries Inc. Integrated circuit structure incorporating non-planar field effect transistors with different channel region heights and method
US10325811B2 (en) * 2017-10-26 2019-06-18 Globalfoundries Inc. Field-effect transistors with fins having independently-dimensioned sections
US10297667B1 (en) 2017-12-22 2019-05-21 International Business Machines Corporation Fin field-effect transistor for input/output device integrated with nanosheet field-effect transistor
US10593598B2 (en) * 2017-12-23 2020-03-17 International Business Machines Corporation Vertical FET with various gate lengths by an oxidation process
US11257928B2 (en) * 2018-11-27 2022-02-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method for epitaxial growth and device
US11011517B2 (en) 2019-01-02 2021-05-18 International Business Machines Corporation Semiconductor structure including first FinFET devices for low power applications and second FinFET devices for high power applications

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4996574A (en) * 1988-07-01 1991-02-26 Fujitsu Limited MIS transistor structure for increasing conductance between source and drain regions
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
CN1507063A (zh) * 2002-12-06 2004-06-23 台湾积体电路制造股份有限公司 使用多栅极晶体管的互补金属氧化物半导体晶体管反向器

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6288431B1 (en) * 1997-04-04 2001-09-11 Nippon Steel Corporation Semiconductor device and a method of manufacturing the same
EP1091413A3 (en) * 1999-10-06 2005-01-12 Lsi Logic Corporation Fully-depleted, fully-inverted, short-length and vertical channel, dual-gate, cmos fet
US6252284B1 (en) * 1999-12-09 2001-06-26 International Business Machines Corporation Planarized silicon fin device
US20020011612A1 (en) * 2000-07-31 2002-01-31 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP4044276B2 (ja) * 2000-09-28 2008-02-06 株式会社東芝 半導体装置及びその製造方法
US6562665B1 (en) * 2000-10-16 2003-05-13 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology
US6657259B2 (en) * 2001-12-04 2003-12-02 International Business Machines Corporation Multiple-plane FinFET CMOS
US6706571B1 (en) * 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
US6864519B2 (en) * 2002-11-26 2005-03-08 Taiwan Semiconductor Manufacturing Co., Ltd. CMOS SRAM cell configured using multiple-gate transistors
US6645797B1 (en) * 2002-12-06 2003-11-11 Advanced Micro Devices, Inc. Method for forming fins in a FinFET device using sacrificial carbon layer
US6762448B1 (en) * 2003-04-03 2004-07-13 Advanced Micro Devices, Inc. FinFET device with multiple fin structures

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4996574A (en) * 1988-07-01 1991-02-26 Fujitsu Limited MIS transistor structure for increasing conductance between source and drain regions
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
CN1507063A (zh) * 2002-12-06 2004-06-23 台湾积体电路制造股份有限公司 使用多栅极晶体管的互补金属氧化物半导体晶体管反向器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9418903B2 (en) 2014-05-21 2016-08-16 Globalfoundries Inc. Structure and method for effective device width adjustment in finFET devices using gate workfunction shift

Also Published As

Publication number Publication date
TWI289354B (en) 2007-11-01
WO2004100290A3 (en) 2005-02-24
DE602004015592D1 (de) 2008-09-18
EP1620891A2 (en) 2006-02-01
ATE403937T1 (de) 2008-08-15
KR20060004659A (ko) 2006-01-12
EP1620891B1 (en) 2008-08-06
CN1784782A (zh) 2006-06-07
US6909147B2 (en) 2005-06-21
TW200507265A (en) 2005-02-16
KR100690559B1 (ko) 2007-03-12
EP1620891A4 (en) 2007-03-28
WO2004100290A2 (en) 2004-11-18
US20040222477A1 (en) 2004-11-11

Similar Documents

Publication Publication Date Title
CN100466229C (zh) 多高度鳍片场效应晶体管及其制造方法
US10974433B2 (en) Gate-all-around fin device
US7960232B2 (en) Methods of designing an integrated circuit on corrugated substrate
US7265008B2 (en) Method of IC production using corrugated substrate
US7247887B2 (en) Segmented channel MOS transistor
US7534669B2 (en) Method and structure to create multiple device widths in FinFET technology in both bulk and SOI
US7368787B2 (en) Fin field effect transistors (FinFETs) and methods for making the same
JPH02134871A (ja) 半導体装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20170106

Address after: Grand Cayman, Cayman Islands

Patentee after: INTERNATIONAL BUSINESS MACHINES Corp.

Address before: American New York

Patentee before: Globalfoundries second U.S. Semiconductor Co.,Ltd.

Effective date of registration: 20170106

Address after: American New York

Patentee after: Globalfoundries second U.S. Semiconductor Co.,Ltd.

Address before: American New York

Patentee before: International Business Machines Corp.

TR01 Transfer of patent right

Effective date of registration: 20180328

Address after: Ontario, Canada

Patentee after: International Business Machines Corp.

Address before: Grand Cayman, Cayman Islands

Patentee before: INTERNATIONAL BUSINESS MACHINES Corp.

TR01 Transfer of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090304

Termination date: 20210130

CF01 Termination of patent right due to non-payment of annual fee