CA1190324A - Byte oriented dc balanced (0,4) 8b/10b partitioned block transmission code - Google Patents

Abstract

A BYTE ORIENTED DC BALANCED (0,4) 8B/10B
PARTITIONED BLOCK TRANSMISSION CODE

ABSTRACT

A binary DC balanced code and an encoder circuit for effecting same is described, which translates an 8 bit byte of information into 10 binary digits for transmission over electromagnetic or optical transmission lines subject to timing and low frequency constraints. The significance of this code is that it combines a low circuit count for implementation with excellent performance near the theoretical limits, when measured with the commonly accepted criteria. The 8B/10B coder is partitioned into a 5B/6B plus a 3B/4B coder. The input code points are assigned to the output code points so the number of bit changes required for translation is minimized and can be grouped into a few classes.

Description

Y09~2 W019 3~2~

A BYTE ORIENTED DC BALANCED (0,4) ~B/lOB
PARTITIONED BLOCK TRANSMISSION CODE

BA~XCROUND OF THE INVENTION

Field_of the In~ention The primary purpose of transmission codes i5 to transform the frequency spectrum of a serial data stream so that clocking can be recovered readily and AC coupling is possible. The code must also provide special characters outside the data alphabet for Xunctions such as character synchronization, fxame delimiters and perhaps for abort, reset, idle, diagnostics, etc. Codes are also used, often in combination with signal wave~orm shaping, to adapt the siynal spectrum more closely to specific channel requirements. In most cases a reduction in bandwidth by constraints on both the high and the low frequency components is desirable to reduce distortion in the transmission media, especially electromagnetic cables, or in the band limited receiver, and to reduce the effects of extrinsic and intrinsic noise.

~nother aspect of codes is their interaction with noise and errors in the line digits. The redundancy associated with line codes can be used to supplement other error detection mechanisms or to monitor the quality of the channel with a minimal amount of circuitry.

Such codes generally exhihit the undesirable feature o enlarging error bursts in the decoded data, making detection by a cyclic redundancy check more difficult. A good transmission code should minimize these effects.

For fiber optic links and intra-establishment wire links, interest centers for many reasons on the family of two-level codes. For wire links one prefers codes with no DC and little low frequency S -content in order -to DC isolate the transmission line from the driver and receiver circuitry, usually by transformers, and to reduce signal distortion on the line. Although these actors do not apply to the fiber optic c:ase, good low frequency characteristics of the code are helpful for a number of reasons.

The high gain fiber vptic receivers need an AC
coupling stage near the front end. The control of the drive level, receiver gain, and e~ualization is simplified and the precision of control is improved, if it can be based on the average signal power, especially at top rates. DC restore circuits tend to lose precision with rising data rates and cease to operate properly below the maximum rates for other circuits required in a transceiver. Finally, if the ~ime constants associated with the parasitic capacitances at the front end of a receiver are comparable to or longer than a baud interval, a signal with reduced low frequency content will suffer less distortion and will enable many links to operate without an equalizing cixcuit.

The Manchester and related codes are simple ~wo-level codes and solve the clocking and low frequency problems very well. They translate each bit into two bits or transmission and are a good choice whenever the high clocking rates cause no problems YO9~2~019 in the logic or analog circuits, the transducers or on the transmission line. They also reduce the data transmission rate by a factor of two since they encode 2 bits for every data bit (i.e., rate 1/2).

Simple SB/6B codes translate 5 binary bits into 6 binary digits and raise the number of information bits transmitted per baud interval to 0.833.
Unfortunately, the implementation of a SB/6B code in a byte-orie~ted (8 bit) system causes burdensome complexities. If the encoding and decodlng is done serially, most of the circuits needed have to operate at the baud rate, which sometimes ~s at the technology limits. Also, there is no simple relationship between the byte clock and the coder clock. Finally, if the frames are not multiples of 5 bytes, the character boundaries will not align with the frame boundaries, which is unattxactive, whether corrected or not. If the coding and decoding is done in parallel, there is no simple mechanism to align a byte parallel interface with a 5B/6B coder; the most straightforward way requires shift registers operating a~ the baud rate.

YO982~019 BA.CKGROUND ART

An article by T. Horiguchi and K. Morita, "An Optimization of Modulation Codes in Digital ~ecording," IEEE Transac~ions on Magnetics, Vol.
S MAG-12, No. 6, November 1976, pag~e 740, is in essence a survey article which cites a grea~
many possible formats for run length limited codes having various d, k values and varying coding xates. It is cited for reference purposes, it being noted that there are no codes suggested in this article having parameters even remotely approaching those of the presently disclosed coding system. Similarly the article is not concerned with maintaining dc balance in the resulting code stream.

An article entitled "Encoding/Decoding for Magnetic Rscord Storage Apparatus," by R. C. Kiwimagi, IB~ Technical Disclo~ure Bulletin, Vol. 18, No. 10, March 1976, page 3147, discloses a (0,6) rate 4/5 run length limited code which attempts to maintain a dc balance. It is noted that this code is significantly different from the present coding system in that both the codes produced and the coder configuration are quite different than that o the present invention even if two of the rata 4/5 coders of this reference were connected in parallel to perform an 8/10 codir.g operation.

U. S. Patent 3,798,635 of Candiani, entitled "Channel Monitor for Depressed-Code PCM Transmission System," discloses an 8 bit to 12 bit code expansion system. It does not disclose the present system's dc balanced run length limited codes.

Y09~2-~19 , U. S. Patent No. 3,577,142 o~ McMillin, enti~led "Code Translation System," discloses a system for translating a 12 bit code into a 8 bit code and is cited as background but does not relate -to the present run length limited coding systems.

U. S. Patent No. 3,594,560 of Stanley, enti~led "Digital Expander Circuit," discloses a simple expander for precompressed data and is similar ~o the two patents cited above representatives of the state of the art and is not otherwise related to run length limited coding systems.

An article entitled "Binary Codes Suitable for Line Txansmission," Electronics Letters, Vol. 5, No. 4, pp. 79~81, 20 February 1969, generally describes a DC balanced rate 5/6 and 3/4 codes but does not suggest combining same nor does it show similar embodiment circui~ry.

No prior art is known to the inventors, which partitions an 8 bit code into 5 bit and 3 bit sub-blocks for encoding purposes nor discloses coding circuitry for concurrently doing the logic manipulations for computing the proper code words~ the disparity of said code words and, depending upon the disparity of the preceeding sub~block, concurrently determining whether a given code word or its complement will be coded.

Y()9~32-019 q~

SUMMARY AND OBJECTS OF THE INVENTION

It is a primary object of the present invention t3 provide a coding system comprising a method .and apparatus ~or producing a ~0,4) runlength limited rate 8B~lOB code.

It is a further object to provid~e such a coding system wherein the code produced is DC balanced and capable of opera~ing near the theoretical performance limits for an 8B/lOB codeO This means the code is near optimum for run length and digital sum variation for an 8B/lOB codeO

It is another object of the invention to provide such a coding system wherein each 8 bit input block i5 broken into a 5 bit and a 3 bit sub-block and encoded separately while maintaining both DC balance and runlength constraints across all block and sub-block boundaries.

It is another object of the invention to provide such a coding system whereln the coding hardware performs bit encoding, disparity, and complementation determinations in parallel to minimize encoding time and logic levels.

It i~ yet another object of the invention to provide such a coding sys~em wherein the above logic, disparity, and complementation determinations are logically cornhined with the uncoded data bits to provide a coded sub block in a minimum number of logic levels.

It is yet another object of the present coding ~ystem to prov:ide a plurality of special purpose control characters such as commas, delimiters, idle characters, etc. by using the extra bits in the coded blocks whereby the special characters may be readily distinguished from data, while at the same time maintaining the DC balance and run length limitations in such characters.

The objects, eatures and advantages of the present invention are realized by utilizing a (0,4) run length limited rate 8B/lOB code which, although somewhat less efficient than for example a rate 5B/6B code, nevertheless has a number of other better coding features and transmission parameters in the code. A more serious objection in the past to 8B/lOB codes has traditionally been the complexity of the coder and decoder circuits.

The coding system set for~h herein, as embodied in the disclosed method and apparatus, substantially alleviates the problem of coder/decoder complexity by partitioning the 8 bit blocks to be encoded into sub-blocks, specifically 5B/6B and 3B/4B
blocks. Coders for these blocks in~eract logically to provide a 8B/lOB code with excellent AC
coupling char~cteristics and timing properties.

7a In one aspect o:E the invention there is provide~ a method for producing a DC balanced (0,43 run length llmited ra-te 8B/lOB code from an unconstrained input data stream comprising a multiplicity of 8 bit data blocks, said method including partitioning the 8 bit block into two sub-blocks consisting of 5 and 3 contiguous bits, examining each sub-block to determine if any of the individual bits require alteration and altering predetermirled bits based on sald determination to produce an alterrlate code pattern, determining the disparity tD0) of lhe current output sub-block being coded, ascertaining the disparity (D~l) of the last non-zero sub-block cod.ed and selecting a first code pattern as the current output sub-block for certain of the output sub-blocks if the last non-zero disparity in -the output code pattern was of a first polarity, assigning the complement of said first code pattern if the last non zero disparity was of the opposite polarity.

In another aspect of the invention there is provided a binary data encoding apparatus for producing a DC balanced (0,4) run length limited rate 8B/10~ code from an unconstrained input data stream including means for supplying consecutive 8 bit data blocks to said apparatus~
means for partitioning the 8 bit input block into two sub-blocks consisting of S and 3 contiguous bits, means for testing each input sub-block to determine if any of the individual bits require alteration during encoding and altering predetermined b.its based on said determination to produce an alternate code pattern from said input bit pattern, means for determining the disparity (D0~ of the current output sub-block being coded, means for determining the disparity (D~l) of the last non-zero sub-block coded and generating a first code pattern as the current output sub-block for certain of the output sub-blocks if the last non-zero disparity sub-block in the output code stream was of a first polarity, means for generating the complement of said fi.rst code pattern if the last non-zero disparity sub-block was of the opposite polarity.

Y~9-82-019 f~

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 comprises a functional block diagram and data flow d.iagram for the coding system of the .present invention.

FIG. 2 is a disparity versus time graph for the coding system of the present invention illustrating the DC balance maintained during the coding processing.

FIG. 3 comprîses a logical schematic diagram which perEorms the determination of the S~/6B
"Classifica~ion: L functions" in the encoder.

FIG. 4 comprises the logical schematic diagram of the circuitry which computes the 3B/4B
"Classification and the S function" in the encoder.

lS FIG. 5 is a logical schematic diagram of the circuitry which computes the "Disparity"
Classifica~ions in the encoder.

FIG. 6 comprises a logical schematic diagram o~ the circuitry which performs the control of Compl~mentation in the encoder.

FIG. 7 is a logical schematic diagram of the 5B~6B
encoder sub block.

FIG. 8 comprises a logical schematic diagram of the 3B/4B encoder sub-block.

FIG. 9 comprises a timing diagram for the encoder clock.

FIG. 10 comprises a logical schematic diagram for computing the P functions ln the decoder.

FIG. 11 is a logical schematic d:iagram of the -circuitry for performing the 6B Classiflcation and the K function computation in the decoder.

FIG. 12 comprises a logical schematic diagram of the circuitry which performs the 6B/SB
decoding in the decoder.

FIG. 13 comprises a logical schematic diagram of the circuitry which performs the 4B/3B decoding in the decoder.

DESCRIPTION OF T~IE PREF:E~RRED EMBODIMENT

General Dlscussion of the Codln~
5~=

As noted above, the stream of signals transmitted down a channel must be constrained so that enough transitions for timing recovery and little or no DC spectral components are present.

A measure of the energy at and near DC is the digital sum variation or DSV, which is obtained as follows. Each channel symbol (corresponding to a possible signal waveform during a baud) is assigned an algebraic value corresponding to its DC componentO The DSV is deined as the variation in the running sum of the encoded data stream, i.e., the maximum minus the minimum value. For a binary or two level code, the one and zero bits are generally assiyned values of ~1 and -1 respect.ively. In the following, the maximum DSV wi].l be denoted by the symbol L.

~Og82-01~

Note, that the number of levels in the running ~um is L-~l. This is because both the maximum and minimum value are included (see FIG. 2).

In the present usage, run length is defined as the number of identical con~iguous symbols which appear in the signal stream. For a binary code, the run length is the number o contiguous ones or zexos arter encoding. What is o interest is the shortest (X) and the longest (Y) run lengths that appear.
These two parameters are oten given in the form (d,k) where d - X-l and k = Y-l. The (d,k) representation gives the minimum (d) and maximum (k) number of bauds between unequal symbols. For an ~Q,3~ code, for example, any 5ymbol can be followed by no more ~han 3 contiguous identical symbols, for a maximum run length of 4. Codes designed for digital transmission usually have a parameter d of zero. The preferred codes for magnetic recording, on the other hand, have usually a parameter value d o 1 or greater, i.e., the minimum spacing between transitions is longer than a baud interval.

A basic principle embodied in the present invention is the partitioned block format. Due to reasons connected with error propagation, it is desirable to encode 8 bits at a time in code words of 10 bits to be transmitted, rather than 4 into S. However, a nonlinear encoding of eight bits such as tha~
described here presents dificulties in implementation, as well as the likelihood that a single error in detection will result in eight erroneously decoded data bits. These problems are solved via the partitioned block format: tha~ is, the eight bits are encoded using coders producing 3S less than 10 bit outputs. These coders interact Y098~-019 so as to yield the desired code words. The result is a coder whose coding rate, complexity and error propagation are near the theoretical limits, and which has ancillaxy benefits in flexibility of adaptation to various situat:ions. Other partitions beside the 5/6, 3/4 were considered in the design proven, but all appear to have disadvantages in error propagation and other criteria.

~ ed 8B/lOB
Coding S~stem The ollowing is a detailed description of the 8B/lOB lO,4) code of the present invention with a DSV=6, which can be implemented with a modest amount of circuitry. The code is near the theoretical limits in terms of the commonly used criteria of Digital Sum Variation and maximum run length. Beyond the 256 code points needed for the encoding of a byte of data, the code, as disclosed contains also 3 synchronizing and 9 other special characters for use as frame delimiters and other control functions. If one includes the 12 special characters, the coding efficiency amounts to 0.8066 bits per baud:

{LOG2 (256 -~ 12)} : {LOG2 1024} = 0.8066 The encoder implementation assumes a parallel byte wide interface for data. A serial implementation is possible; however~ this code is primarily intended for links operating at or above a few Mbit/sec, where there is incentive to minimize the number of logic circuits operating at the baud rate and to separate out as many lower speed circuits as possible for implementation fq,. ~ q~ f~

in a denser, lower cost technology. The encoder and decoder circuits operate at the byte rate.

Referring briefly to FIG. 1 the overall functiona1 organi~ation of the encoder o the present invention is shown. The FIGURE also represPnts in essence a data flow chart for the encoding sytem.
It is assumed that 8 bit bytes o~ parallel data enter the adaptor interface 10 at the top. It will be well understood that the data could be provided on parallel lines from an originating system or could be the output of a serial to parallel converter which accumulates data in 8 bit blocks and transfers it to the adaptor interface 10 in parallel. The 8 input data bits are clearly shown as ABCDE and FGH. Control bit K as shown will indicate special characters. The first 5 data bits ABCDE are ga-t~d into the logical function encoder 12 or the 5 bit sub block and bi-ts FGH are ga~ed to functional encoder 14 for the 3 bit sub-block. The logical functions these blocks perform is set forth in the "classification" column of Table I labelled "bit encoding." The disparity control 16 performs the logical determinations specified in the "disparity" classification column of Table I. The outputs of bloc~s 12, 14 and 16 together with the 5 bit and the 3 bit data ABCDE
and FGH respectively proceed to the encoding switch 18 where the final encoding operation takes place to produce the encoded sub-blocks abcdei and ghj. A description of the Logical operations and circuitry for performing the 'bit encoding,' the 'di~parity' determinations and the complementation decisions will be set forth more fully subsequently.

To summari2e the communications Adapter interface 10 consists o the 8 data lines ABCDEFGH (note the upper case notation), a control line K, and a clock llne CLK operating at the byte rake. The control line K indicate~ whether the lines A through -H represent data or control informatiorl such as frame delimiters and a limited set of other special characters.

For encoding purposes, each incoming byte is partitioned into two sub-blocks, The 5 binary L0 lines ABCDE (see FIG~ 1~ are encoded into ~he 6 binary lines abcdei (note the lower case notation), following the directions of the 5B/6B logic functions and the disparity control. Similarly, the three bits FGH are encoded into fghj. The 5B/6B
and 3B/4B encoders operate to a large extent independently o each other.

The disparity of a block of a data is the dlfference between the number of ones and zeros in the block; positive and negative disparity numbers refer to an excess of ones or zeros xespectively. For both the 6B = abcdei and 4B = fghj sub-blocks the permittad disparity is either zero or ~2 or -2. As an example, a 6B sub~block containing 4 ones and 2 zeros has a disparity of ~2. The coding rules require that the polarity of non-zero disparity blocks must alternate. For this purpose, there is no distinction made ~etween 6B and 4B sub-blocks.

Non-zero disparity code points are assigned in complementary pairs to a single data point. The encoding functions generate one of them; if it violates the alternating polarity rule, the `complete sub-block is inverted in the encoding switch to conform with the required disparity.

Yo982-~01~

1'1 Dlspari-ty and polari-ty determination in the 6B
encoder is followed by the corresponding operations of the 4B encoder, then the running disparity parameter is passed along for encoding of the next byte.

The majority of the coded sub-blocks are of zero disparity and are, with some excep-tions, independent of the running disparity, i.e., they do not have a complementary alternate since they don't need one.

The 10 encoded lines abcdeifghj would normally interface with a serializer for subsequent transmissionO The 'a' bit must be transmitted first and 'j' last.

The 8B/lOB encoding is accomplished by encoding the bits ABCDE of the input byte into the line digits abcdei in a 5B/6B encoder following the coding plan and rules specified Table I, and the bits FGH
in a 3B/4B encoder into the line digits fghj following the rules of Table II.

Referring now to Table I, the first column headed by NAME gives the 32 decimal equivalents for the input lines A~CDE, assuming A is the low order bit and E the high order bit. For regular data (D.x) the line K must be held at zero. A few code points can be part of special characters, which are recognizable as other than data; such code points are nam~d D/K.x or K.x and have an x or 1 in column K. To encode special characters the K line must: be one. The code points designated K can only be special characters while the ones designated D/K can be either depending on the setting of the IC line.

Y~)9~ 01~

In the CLASSIFICATION column, the entry I,04 means that there are no ones but 4 zeros in ABCD; L13 means that there is 1 one and 3 zeros in ABCD, etc.
The letter L indicates that this logic function or -cl~ssification is part of the 5B/6B encoder.
Analogous functions are defined for the 6B/5B decoder in Table IV and labelled PO An accent to the right of a symbol is used to represent complementation; thus E~ means the complement of E.

In the column under the left 'abcdei' heading there are all the code points listed which are generated directly by the 5B~6B logic functions from the ABCDE inputs. The coding table was designed 50 that a minimal number of bits need to be changed on passing through the encoder, and such that the changes which are required, can be classified into a ~ew groups applicable to several code points. A11 th~ bits in Table I, in the "abcdei" column which require action by the 5B/6B
logic functions other than complementation of the complete sub block, are in bold type, assuming that the extra digit i is normally added with a value of 0.

When the inputs meet ~he logical conditions listed in the left sub-column under the column marked CLASSIFICATIONS, BIT ENC, then the bold type bits are changed ~o ~he values show~ in the let abcdei column; e.g., if L04 holds, then the b and c digits axe forced to ones as shown for D.0 and D.16. The second en~ry in the CLASSISFICATION, BIT ENC. column or D.16 (L04-E) and D.31 (L~0-E) applies to the i digit. For lines with no classification entry, the ABCDE bits translate unchanged into abcde and the added i bit is a zerc.

I-t should be understood that the logic statements or definitions pertaining to the various data input configurations as specified in the two columns marked 'bit encoding' and 'disparity' represent the s logic which the logic function circui-try of blocks 12 and 14 and the disparity control circuitry of bloc]c 16 (all on FIG. 1) must perform. The actual logic operations are perormed in the detailed logic circuitry set forth in FIGS. 3, 4, 5 and 6 which are all described more fully subsequently.
In these tables the data bits or values are clearly marked and defined by i.e., ABC or their complements A'B'C' as well as the particular logic functions wherein a is an AND function and a + denotes an OR function, etc. The same defintions apply also to the logic functions and explicit circuitry se-~ forth in Table II, IV and V.

The alternate abcdei column to the right of Table I shows the complementary form for those ABCDE inputs which have an alternate form.
Individual 6B (and 4B) sub~blocks are complemented in conformity with the disparity rules. At all sub-block boundaries the running disparity is either + 1 or - 1 and never zero (see FIG. 2).
FIG. 2 is described more fully subsequentlyn The column D-l indicates the required running disparity for entry of the adjacent sub-block ~o the right (i.e., the next sub-block to be coded).
An x in the D~l column means that D-l can be +
or -. Stated differently the disparity of the current sub-block is zero. In this code the polarity of th~e running disparity at sub-block boundaries is identical to the polarity of the most recent non-zero disparity block.

L ~

As an example for encoding of the first line D~0 of Table I: If the running disparity matches D~ , then the output to the encoder will be 011000; otherw1se the entire sub~block is complemented to 100111.

The D0 colu~n indicates the disparity of the encoded sub-block to the left (the sub-block being coded), which is either 0, ~2 or -2. The! disparities (i.e., columns D-l and D0) for the "alternate"
code points on the right side of Table I and II `
are exact complements of those to their left and are not shown in the Tables.

Similar to bit encoding, the encoder hardware determines directly from the ABCDE and K inputs the disparities of a sub-block without really counting ones and zeros. The respective logic func~ions performed for classification of code words in terms of disparity requiremen~s are shown in the separate column în Table I marked "Disparity."

In Table I, line D.7, a pair of zero disparity 6B
sub-blocks is assigned to a single data point with an entry disparity constraint similar to those appLicable to non-zero dispair~y sub-blocks.
This coding feature reduces the maximum digital ~5 sum variation ~rom 8 to 6 and, combined with an analogue rule in the 3B/4B encoder for D/K~x~3 o Table II, (explained urther subsequentl~)~
eliminates all sequences of run length 6 and most of those with run length 5.

The technique of assigning a pair of complementary zero disparity sub-blocks to a single code point is also used uniformly for all 4B suh-blocks which are part of a special character as shown YO382-01.

1~
in Tables II and III for the ~pecial chaxacters designated as X.28.1, K.28.2, K.28.3, K.28.5 and K.28.6.

Table II follows the conventions and notations of 5 Table I. In Table II some lines have 2 entries in the column for the classification of disparity;
the left classification refers to the entry disparity D-l and the right one to D0.

The encoding of D.x.P7 (Primary 7) and D/K~y.A7 (Alternate 7) requires an explanation. The D/K.y.A7 code point was introduced to eliminate the run length 5 sequence in digits eifgh. The A7 code replaces the P7 encoding whenever:

[(D-l-+) AND (e=1=0)] OR ~(D-l=-) AND (e=i-l)] OR
(K -1) Note, that FG~ - 111 is always translated into fghj - 0111 or the complement if K = 1.

The D/K.y.A7 encoding can generate a run length 5 sequence across the trailing character boundary in the ghjab bits; however, this sequence is preceded by a run length of only 1 in digit f r with one exception: If the leading character is the special char~cter K.28.7, a run length S
sequence across the trailing character boundary is preceded by another run length S sequence in sdeif. For the significance of these distinctions see the following discussion of special characters.

The zero-disparity 4B sub-blocks of K.28.1, K.28.2, K.28.5 and K.28.6 are handled .similarly to D/K.x.3 with respect to complementation in order to generate sorne special sharacters with byte YO98~019 synchronizing or comma properties. The first number (28) is the decimal equivalent for abcde, the second number is for the decimal equivalent of bits fgh, x is for don't cares.

Special characters are defined here as extra code points beyond -the 256 needed to encode a byte of data. They can exist because of the 2 extra bits inserted by the encoding process (i.e., 8 bit~
expanded to 10 bits).

They are generally used to establish byte synchronization, to mark the start and end of frames and sometimes to signal control functions such as abort, reset, shut off, idle and link diagnostics. The set of 12 special characters shown in Table III can be generated by the coding rules defined in Table I and II. This set of special characters includes the most useful ones from a larger set which could be defined, if needed.
They all comply with the general coding constraints of a maximum run length of 5 and a maximum dlgital sum variation of 6.

The first group of 8 special characters K.28.x, Table III, can be recognized as other than data by observing that abcdei = 001111 or 110000. In data we have never c-d=e=i.

The second group of 4 special characters K.x~7, Table III, is characterized by eiEghj = 101000 or 010111. The distinction from data is the encoding of FGH into A7 (0111 or 1000), where according to Table II, P7 (1110 or 0001) would be used for data, or valid data fyhj = 1000 requires that ei = 00 and fghj = 0111 must be preceded by ei = 11.

A comma indicates the proper byte boundaries and can be used for instantaneous acquisition ox verification of byte synchronization. To be useful~ the comma sequence must be singular and occur with a uniform -alignment relative to the byte boundaries; in the absence of errors the comma must not occur in any other bit positions neither within characters nor through overlap between characters. Three characters in this code (K.28.1, K.28.5~ K28.7) have comma properties; ~hey are marked with an asterisk in Table III and the singular sequence is printed in bold typeO These three characters are also the most sui~able delimiters to mark the start and end of a frame.

The singular comma in this code is a sequence of run length 2 or moxe ending with digit b followed by a run length 5 sequence; where this second sequence is not permitted to be the RL>2 sequence of another comma; in other words, if two or more RL>2/~L5 sequences o~erlap, only the first, third or any odd nun~ered one is recognized as a comma.
This rule is necessary, because in some situations the K.28.7 comma is followed by another run length 5 sequence in digits ghjab.

A sequence o contiguous K.28.7 characters would generate alternating RL=5 sequences of ones and zeros, which is not useful for character synchronization and is poor for bit clock synchronization. For this reason, no adjacent K.28.7 characters are allowed.

Despite the restrictions placed on it, the K.28.7 comma is often prefexred over the other two, because in the synchronized state no single error Yoss2-nls J~

can generate a valid K.28.7 from data. To get the same level of immunity from noise with the other two commas one can define the frame structure so the delimiters are always followed by a 6B sub block with non-zero disparity.

The parameters used in the present description to describe the spectral properties o the code are the digital sum variation, the disparity, and the run length.

The maximum DSV between arbitrary points in this code is 6. Sometimes the DSV i5 quoted with reference to specific bit positions, such as the end of a character, and a lower figure usually xesults. For the code described here the maximum DSV between any two i/f or j/a bit boundaries is 2.

As described previously, the term disparity is used here to de~ignate the excess of one bits over zero bits in a defined block of digits or the instantaneous deviation from the long-term average value of the running digital sumO All 6B and 4B
sub-blocks individually and the complete 10-baud characters have a disparity of either 0 or ~2, ine., each valid character in the lOB alphabet has ei~her 5 ones and 5 zeros, or 6 ones and 4 zexos, or 4 ones and 6 zeros.

It is instructive to plot the disparity as a function of time or baud intervals as is done in FIG. 2, where each one bit is marked by a line segment extend:ing over 1 baud interval and xising at a 45 angle; conversely, a zero bit is represented by a falliny line. As an example, staxting at the circled +l disparity value on the left most j/a bit bourldary, a 110100 digit pattern would lead alony -the upper contour to disparity = +l at the i/f bit boundary. Alternatively, starting from the same point, a pattern such as, for example, 001010 (abcdei) leads to a disparity of -1 at the 1/f bit boundary. All data characters and speclal characters of Tables I, II and ~II are represented in FIG. 2. The bold lines represent the comma sequence.

From the diagram it is immediately evident that the maximum DSV between arbitrary points is 6.
Since the disparity is bounded, the code is free of any DC component (i.e., DC balanced).

FIG. 2 also reveals some of the dynamics of the disparity parameter, i.e., how long it can remain at extreme valuesO Thus, the disparity of this code cannot exceed ¦2¦ for longer than 2 baud intervals; similarly, it cannot remain above ¦1¦
in excess of 6 baud inter~als.

On the other hand, the disparity can remain non-zero for the duration of a complete frame minus 10 baud intervals. It is readily seen from FIG. 2 just what the necessary conditions for this are. If, for example, the data portion of the frame starts with a Disparity of ~1 and throughout the frame (abcdei = 110100, OR 101010, OR 101100) AN~
Ifghj = 1010) the diparity will not return to zero until the ending delimiter; the delimiters as described in 3.2.3.1 all contain at least one nonzero-disparity sub-block and cross the zero disparity line in the center of the character between the e and i bits, as shown by the bold lines. The dynamics of the disparity parameter are relevant to the design of the AC circuits associated with the transmitter and receiver.

The run length was defined previously, as the number of contiguous identical symbols; since the code at hand is a binary or two level code, the run length is simply the number of contiguous ones or zeros after encoding. What is of interest is the shortest and the longest run length, which are one and five in this code.

FI~. 2 also shows, which bit positions could poten~ially be part of a run length 5 sequence.
Potential RL = 5 sequences start with bit positions c~ e, g and j. However, inspection of Table I shows that the 6B alphabet does not include any code points for which a=b=c=d and that c=d=a=i is confined to th~ K.2B.x special charac-ters; these constraints render impossible any RL=5 sequence starting with j and limit those starting with c to the comma sequences listed in Table III. The RL=5 data sequence starting with e is eliminated through -the alternate code point D.x.A7 of Table II, which in ~urn is the sole generator of the RL-S
sequence staritng with g; note, however, that this sequence i5 always preceded by RL=l except when overlapping with the K.28.7 comma.

Yo982-01

2~
Single errors or short error bursts in the encoded line digits of any block code can generate a longer error burst in the decoded message. For the 8B/lOB code proposed here the effects of line 5 digit errors are always confined to the 6B or 4B
sub-blocks in which they occur and generate error bursts no longer than 5 or 3, respectively, from a single line digit error. This derives from the fact, that each 6B or 4B sub-block i5 uniquely decodable on the basis of just the values belonging to that sub~block and wi~hout any reference to disparity or other extraneous parameters. The only exceptions are the special characters Ko28~1~
K.28.2, Xo28.5, X.28.6, for which the decoding of the fghi bits i5 dependent on the abcdei bits;
however~ adverse effects from this are limited since special characters usually appear only at specified slots with respect to the frame boundaries and often are not covered by the CRC.

The inherent redundancy of the code can be used ~cr error detection. Errors in the line digits will often generate invalid characters or violations of the disparity rules. Simple circuits (not shown in this application) can monitor for such irregularities. Generally, whenever the number of erroneous ones ln the line digits of a frame is not equal to the number of erroneous zeros, it will be detected as a code violation and in many of the other cases as well.

From the previous section, one can conclude, that the CRC used with this code should detect at least any co!mbination of double errors in the line digits, if it is to make a significant impact on the combined guaran~eed level of error detection. A double error in the line digits Y0~82-Olg can generate in the worst case 2 error bursts of length 5 each after decoding. Fire codes are well suited for ~his application. Peterson and Brown teach in "Cyclic Codes for Error Detection,"
Proceedings IRE, Vol. 49, pp. 228-235, January 1961, Theorem 8, how to specify generat:or polynomials for cyclic codes with the capability to detect two ~urst of errors. With 16 check bits two bursts of combined length ten or less can be detected in 10 frames as long as 142 bytes; 24 check bits can accomplish the same thing for frames as long as 36862 bytes. Other intermediate options are available, e.g., there is a polynomial of degree 24 which can detect two bursts of combined length sixteen in frames up to 958 bytes long.

A CRC can generally detect any single errox burst of a length, which does not exceed the number of check bits. With the 8B/lOB code described here t any single error burst in the encoded digits of leng~h 15 or less cannot grow to more than 16 bits after decoding. Similarly error bursts of length 25 and 35 in the encoded bits translate into exror bursts no longer than 24 and 32 bits, respectively, a~ter decoding.

In summary one can conclude, that for all frame lengths of practical interest a 24 bits or longer Fire code combined with the inherent error detection capability of the 8B/LOB code can detect any three errorq in the line digits, provided the beginning and end of the frame have been correctly established.

An 8B/lOB encoder, serializer, deserializer and decoder thave been built and opexated as part of an experimental 200 Mbaud fiber optic link.
The circuit diagrams qhown in FIGS. 3-8 and 10-13 YO98~-019 include some slight streamlining changes for the purpose of clarity. The Tables I, II and III
should be referred to for details of the more fundamental logic. The plus and minus signs associated with the line names of the logic diagrams refer to the more positive or more negative line levels, respectively; e.g., +L13 in FIG. 3, is at the more positive level, i L13 is true; -B
is at the more negtakive level, if BY1.

The encoder and decoder have been implemented with MECL 10000 Series circuits fxom Motorola Corp.
All flip~flops shown are of the positive edge triggered type.

The encoder is clocked by a byte rate clock derived from the transmitter (shown in FIG. 9). The byteclock ~+SBYTECLK, S for Sender) is also passed on to the data source buffer, which responds after each positive clock transition with a new byte ABCDEFGH K on 15 parallel lines labelled +A, -A, +B, -B, ~C, -C, +D, -D, +E, -E, ~F, +G, +H, ~K, -K. The encoded bytes are delivered -to the output buffers in FIGS~ 7 and 8. The lines -a, -b, -c, -d, -e, -i are updat~d after each positive transition of the +SBYTECLK (FIG. 7), the lines -f 9 -g~ -h, -j after posi~ive transitions of the -SBYTECLK (F LG. 8 ); this staggered transfer is possible because of the partitioned skructure of the code.

The circuitry of FIG. 3, performs the yeneration of some of the basic classifications of Table I
(Encoder: L Functions), from the encoder inputs.
For an explanation of the imput and output notations refer to the previous description of Table I.

YO9~2-019 t~

For a detailed description o -the logic convention utilizPd in ~hese FIGURES reference should be specifically made to an article entltled "Documentation Standards Clarify Design," by -John F. Wakerly, in Computer Design, February 1977, pages 75 85 (specifically see page 77). This article generally discusses the use of dot inputs on various logic circuit devices and also the use of positive and negative inputs for certain logic design applications. Also see "198~
Supplement of the TTL Data Book for Design Engineers," second edition, publish~d by Texas Instruments Coxporation, from pages 321-325.
The reference extends the discussion in the reference set forth above and indicates the use of the arrows on inputs and outputs as a substitute for the above described dots on the inputs and outputs where essen~ially complemen~ary or negative value inputs and outputs are required or design purposes.

The circuits of FIG. 4 generate the classificatio~s of Table II. The F, G, H and K inputs are buffered. -PDL6 or NDh6 is at the down level, if the running disparity as seen on the transmission line following the i bit of the 6B sub-block is positive or negative, respectively, as illustrated in FIG. 2. PD~6 and NDL6 axe generated in FIGo 6.
It should be noted that the number 4 appearing with certain of the bit values (F4, G4, H4, K4) distinguishes the output of the 4 buffers from their inputs and are valid during 3B/4B encoding.

The circuitry of FIG. 5 implements the disparity classifications of both Tables I and II. All inputs are from FIG. 3 a~d 4 or the data source, except for (L13~D E) which can be found in FIG. 7. The Yo~2 -01~

3~'~

mnemonics for the outputs are as follows- P for Positive, N for Negative, S for Sender as a distinction from analogue functions labelled R
in the decoder at the receiving end; D-l and D0 refer to the respective columns in Table I and II;
the number 6 associates a function with 5B/6B
encoding and Table I, the numbe.r of 4 with 3~/4B
encoding and Table II. As examples, ~PD-lS6 is at the up level for any input which has a ~ sign in the D-l column of Table I, +ND0S4 is at the up level for any input with a minus sign in the D0 column of Table II.

The upper flip-flop in FI~. 6 keeps track of the running d.isparity at the end of the i bit and the lower flip-flop does the same for the j bit.
The gates to the right make the decision, whether the alternats, complemented code points of Table I and II apply, on the basis of the running disparity and the D~l entry disparity classifications of FIG. 5. The gates to the left determine how to update the flip-flops taking into account the D0 disparity of the sub-block being encoded, complementation and the running disparity at the end o the previous sub-block. ~PDL4 is at the up level for a positive running disparity.
at the end of the j bit. The 2 flip flops shown in FIG. 6 can be replaced by a single flip~flop, but this requires an additional clockline from the serializer, running at twice the byte rate.

FIG. 7 performs the actual transformation of the 5 input bits ABCDE into the 6 abcdei outpu~ bits according to Table I. The gates to the left of the Exclusive-Or gates (E) bring about all ~he bold type bit changes o~ Table I.

The circuitry of F-LG. 8 performs the 3B/4B encoding according to Ta~le II.

FIG. 9 shows the timing relationship between the ~vents in the encoder.

Logic ~ircuits for the Decoder (FIGS. 10-13) The logical functions for the decoder and their classi~ications are defined in Table IV and V. For decoding, the i and the j bits are dropped and some of the remaining bits are complemented as indicated by bold 0 and l entxies in the tables.

The circuitry of FIG. lO generates some fundamental logic functions for decoding, very similar to FIG. 3 for the encoder. The inputs for FIG. 10 are the encoded bits and are normally assembled at the receiving end of a transmission link by a Deserializer in a 10 bit wida parallel register ~not shown).

The circuitry of FIG. ll executes the decoding classifications of Table IV and the K function, which indicates a special character, as stated in explicit form at the bottom of Table V. The two input functions dependent on the ghj bits are coming from FIG. 13.

The circuitry o~ FIG. 12 uses the logic functions generated in FIG. 11 for the actual 6B/5B decoding according to Table IV.

The circuitry o FIG. 13 shows 4B/3B decoding according to Table V.

All the encoder and decoder circuits of FIGS. 3-8 and 10~13 are operating at the byte rate. An yo~2 Ol9 '3~

examination of the critical delay shows that the gate delays Eor the encoder and decoder should not exceed 1 baud interval.

-In order to determine the circuit count, each s exclusive OR gate (E) is counted c19 3 gates. The gate count for the encoder (FIGS. 3-8) is 89 gates and 17 flip-10ps; the decoder (FIGS. 16~19) requires 79 gates and 9 flip flops. At low and medium data rates, where the gate delays are much less than a baud .interval, some trivial design changes can significantly reduce the circuit count. For one, when the encoding and decoding delays are only a fraction of a byte time the 10 buffer flip~flops at the output of the decoder (FIGS~ 11, 12, 13) and the encoder huffers of FIG. 7 or FIG. 8 or both, can be Pliminated. Therefore, at the low end an encoder and dPcoder can be implemented with an appropriately lower circuit count.

It would be obvious to extend the teachings of the present coding system to other block sizes. Thus, if one wanted to encode 11 bits (8 daka, 3 control) for example, using the teachings of the present coding concept, the input block would be broken into three sub blocks to produce a 5B/6B, 3B/4B, 3B~4B parallel encoder obeying all of the present run length and disparity constraints.

INDUSTRIAL APPLICABI~ITY

While the intended application of the present coding system is primarily high speed computer links, it compares also favorably with Manchester coding in less deman~ing applications. For a gi.ven data rate the clock rate :is reduced to 62.5~ of the rate require~ for Manchester coding, while most of ~0982-019 the important attributes of the Manchester code are preserved.

The main attraction of the present 8B/lOB coding system compared to, for example, Manchester code for high speed fiber optic links is the reduction in the clock rate by a factor of 0.625, corresponding reductions in the required speed of the logic gakes and the risetimes of the fiberoptic components. Depending on the specific data rate, the lower ratio of baud rate to byte rate helps single technology and single chip implementations of the logic functions associated with the com~tunications adapter including coder/decoder, serializer, deserializer and clocks, resulting in some Iogic cost savings despite the higher circuit count. Manchester coding more often requires extra high speed circuits in the clocking and coding area.

The 8B/lOB code of the present invention brings with it also a welcome improvement in the fiberoptic power budget by +1.6 dB for a PIN sensor with bipolar front end and by +3.5 dB with an FET front end resulting from the reduced bandwidth at the receiver amplifier. For LED links an additional 1.5 db gain or more i~ the power budget is realized, because the lower baud rate makes more powerul LED sources available. The LED device designer has to make a trade-off between power and bandwidth.
Published diagrams, which ar~ supported by theory and practical experience, show the log ~Optical Power) verstls log (Bandwidth) of LED devices as straight lines falling at the rate of about 7.5 db/decade for frequencies up to 140 M~z and almost twice as steep beyond thak.

Y~982-01 3~
For typical copper wire transmission lines the attenuation increases proportionally to the square root of frequency in the area above lOOkHz.
Therefore, -the lower baud rate of the 8B/lOB code results in approximately 26% less attenuation than Manchester code. On the other hand, the increased run length results in ~lore timing distortion, but adverse effects from this can be avoided to a great extent by signal shaping at the transmitker, by equalization and with better performing timing circuits.

Communication links using multipair cables and operating at several Mbit/s are often limited in d.istance by near end crosstalk (NEXT). The signal to NEXT margin is significantly improved by use of the 8B/lOB codeO Consider, as a point of reference a Manchester coded link with 30 dB
attenuation measured at one half the baud rate (1 MHz for 1 Mbit/s Manchester). The attenuation ~0 of a 1 ~bit/s 8B/lOB signal over the same link is reduced to 23.7 dB, increasing the available signal to NEXT margin by 6.3 d~ through lower signal attenuation alone, if the distance is held constant.

An additional marginal improvement is realized through the reduction in the crosskalk noise, because the power spectrum of 8B/lOB coded signals is shifted to lower frequencies. If the NEXT loss for a long line is K~ dB at frequency fO, it can be found for any cther requency, f, by NEXT loss = Ko - lS log10 f/fO

The shape of the power spectrum for the present 8E/lOB signal i.s comparable to the Manchester YO982~019 spectrum, but frequencies are reduced by a factor of 0.625 and for random data the energy i5 shifted even more toward the lower frequencies. Therefore, it can be estimated conservatively that a reduction of the near end crosstalk of ~15 log 0.625) dB = -3.06 dB

results from the frequency reduction. The potential gain in signal to noise ratio over Manchester code is thus 9.36 dB, reduced slightly by highex residual distortion.

3~

Y09~2~019 ~AME ABCDE K CLASSIFICATIONSD-l abcdei DO ~bcdoi BLT ENC. DISPA~ITY ALTER-NATE
D O 00000 0 L04 L22'-L31'.E' ~ 011000 - lOOlll D l 10000 0 L13.E' L22'-L31'~E' + 100010 - 011101 D.2 01000 0 L13~E' L22'.L31'.E' ~ 010010 - 101101 D 3 11000 0 L220E' x 110001 0 D 4 00100 0 L13-E' L22'.L3i',E' + 001010 - 110101 D.5 10100 0 L22-E' x 101001 0 D 6 01100 0 L22.E' x 011001 0 D 7 11100 0 L31-D'.E' - 111000 0 000111 D.8 00010 0 L13-E' L22'-L31'~E' + 000110 - 111001 D 9 10010 0 L22.E' x lOOlOt O
D.10 01010 0 L22~E' ~ 010101 0 D ll 11010 0 ~ 110100 0 D 12 00110 0 L22-E' x 001101 0 D 13 10110 0 x 101100 0 .14 01110 0 ~ 01110~ 0 ~D 15 11110 0 L40 L22'~L31'.E' ~ 101000 - OlOlli D.16 00001 0 L04, L04~E L22"L13'^E ~ 011011 ~ 100100 D 17 10001 0 L13-D'-~ ~ 100011 0 D.18 01001 0 L13-D'-L x 010011 0 D~19 11001 0 x 110010 0 D 20 00101 0 L13-D'-E x 001011 0 D 21 10101 0 x 101010 0 D 22 01101 0 x 011010 0 D/K 23 11101 x L22'oLl31-E - 111010 + 000101 D 24 00011 0 L13-D.E L13-D-E + 001100 - 110011 D 2$ 10011 0 x 100110 0 D 26 01011 0 x 010110 0 D/K 27 11011 x L22'.L13'-E - 110110 ~ 001001 D 28 00111 0 x 001110 0 D~K 29 10111 x L22'.L13'.~ - 101110 + 010001 D/K 30 01111 x L22'.L13'~ - 011110 + 100001 D 31 11111 0 L40, L40~E L22'-L13'-E - 101011 + 010100 K X8 00111 I L22.K K - OOllll ~ 110000 TA~LEI~ 5B/6B ENCODING
!

YO9 8 2 - 0 l 9 3~

IE F~H K CLASSlFlCATlONS D-l f g h j D0 f ~ h j BIT ENC. DISP~'\RITY ALTER-NATE
D/K.x.0 000 x F'~ H' F'-G' + 0100 --101 1 D.x.l 100 0 (F~6C)-H' x 1001 0 D.x.2 0 1 0 0 (F~6G).H' x O 1 01 O
D/K.x.3 110 x F.G -- 1100 0 0011 D/~C.x.4 001 x F'-G' ~0010 -- 1101 D.x.S 101 0 x 1010 0 D.x.6 011 0 x 0110 0 D.x.P7 1 1 1 0 F~C;, F.G.H -- I 110 + oao 1 I:)/K.y.A7 1 1 1 x F~G.H,(S~K) F.(3, F.G.H -- 01 11 + 1000 S = {e.i.(D~ + {e'.i'.(D--1=+)~
K.28.1 100 1 (F~G).H' (F~G)-K ~ 1001 001l0 K.28.2 0 1 0 1 (~sG)~ H' (F~G)-K ~0 101 0 1 01 0 K.28.5 101 1 (F~G)-K + 1010 00101 K.28.6 011 1 ~F~G)~K ~ 0110 01001 K.x RESTRICTED TO K.28 K.y RESWCTEI) TO K.23, K.27, K.28, K.29, K.30 l'ABLE II. 3B/41B ~NCODING

: .
.

.... . _ . ..

NAME: ABCDE FGH K D-1 ab-~dei f gh; D0 O-l abcdei f ghj D0 ALI'ERNATE
K.28.0 00111 000 1 -- 001111 0100 0 * 110000 1011 0~C.28.1~ 00111 100 1 - 0011~ 01 ~ + tl~000 011~K.28.2 00111 010 1 -- 001111 0101 ~ + 110000 1010 --K.28.3 001 1 1 1 10 1 -- 001 1 1 1 0011 ~ ~ l l 0000 1 100K.28.4 00111 001 1 0011110010 0 ~ 110000 1101 0 K.28.5~ 00111 101 1 - 0011111010 + ~ 110000 010l --K.28.6 00111 011 1 -- Q01111 0110 + + 110000 1001 --K.28.7r 00111 111 1 - 0011111000 0 ~ 110000 0111 0 K.28.7 MUST ~OT BE CONTIGUOUS TO ANOTHER K.28.7 K.23.7 11101 111 1 - 111010 1000 0 + 000101 0111 0 K.27.7 11011 111 1 -- 110110 1000 0 + 001001 0111 0 K.29.7 lQlll 111 1 -- 101110 1000 0 ~ 010001 0111 0 K.30.7 01111 111 1 -- 011110 1000 0 - + 100001 0111 0 ~SINGUI,AR COMMA (FOR BYTE SYNCHRONIZATION) T~BLE Ill. SPECLAL CHL~RACTEls5 ~ 5 1) Y0~82~019 NAME a b c d e i DECODINC CL~SS ABCDE K
D0 011000 P22.b.c.(e=i) 00000 0 D.0 lû011 I P22.b'.c'.(e=i) 00000 0 D l 100010 P13.i' 10000 0 D l i)l 1101 P31.i t0000 0 D2 010010 P13-i' 01000 0 D.2 101101 P31.i 01000 0 D.3 1 10001 1 1000 0 D.4 001010 Pl3si' 00100 0 D.4 110101 P31.i 00100 0 ID.5 101001 10100 0 D.6 011001 01100 0 D.7 1 1 1000 1 1 100 0 D.7 000111 P13-cl-e-i 11100 0 D 8 000110 Pl3.i' 00010 0 D8 111001 P310i 00010 0 D.9 100101 10010 0 D.10 010101 01010 0 D.ll 110100 11010 0 D.12 001101 00110 0 D.13 101100 10110 0 D.14 011100 01110 0 D.15 101000 P22-a~c.(eai) 11110 0 D.15 0101 11 P22.a'.c~(e--i3 t l ~ 10 0 D.16 011011 P22.boc.(e=i) 00001 0 D.16 100100 P22.b'.c'.(e=i) 00001 0 D.17 100011 10001 0 D.18 010011 01001 0 D.l9 110010 11001 0 D.20 001011 00101 0 1:).21 101010 10' 01 D.22 011010 01101 0 D/K.23 111010 11101 x D/K.23 000101 P13-e' 11101 x D.24 001100 a'lb'-~'-i' 00011 0 D.24 1 10011 a-b.e.i 0001 1 0 D/K.27 110110 11011 x D/K.27 00l001 P13.e' 11011 x K28 001111 c-d-e-i 00111 1 K.28 110000 c~-d~.e'.i' 1301 t 1 D/IK29 101110 ` 10111 x D/K.29 010001 P13-e' 10111 x D/K.30 01 1 1 10 01 1 1 t x D/K.30 100001 P13~e' 01 111 x 1:).31 10101 I P22~a.c~(e=i) 11 11 1 0 D31 010100 P22-a'sc'-(~=i) 11111 0 TA~LE IY~ 6B/SB DECODING

3~2~

Y0982-0l9 , NAME f ghj DECODING CLAS~; FGH K
D~K x 0 0100 f~oh~ 01)0 x D/K x 0 1(311 f.h.j 000 x D/Kx l 1001 100 x K.28 1 0110 c'-d'Oe'si'.(h~6;) 100 1 I)/Kx2 0101 010 x K.28 2 1010 c'.d'.~'.i'.~h~j) 01 û
D/K.x3 1100 110 x D/Kx3 0011 f~g~-h~; 110 x D/Kx4 0010 001 x D/Kx4 1101 f.g~j 001 x D/Kx.S 1010 101 x K.28 5 01 01 c'~d'se'oi'~(h;~;) 101 D/Kx6 0110 011 x K.28 6 1001 c'.d're'.i'-(h~6j) 011 D x.7 1110 111 0 D x 7 0001 f~g~h~ 111 0 D/Kx7 0111 goh.j 111 x D/K x 7 1000 g~h~ 111 x K ~ (c=d=e=i) OR (P13-e'-irg-h-j) OE~ (P31.e.i'og'~,h'oj') TABLE V. 4B/3B DECODIINlG, K FUNCTIOE~J

.... . _ .

Claims (20)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A method for producing a DC balanced (0,4) run length limited rate 8B/10B code from an unconstrained input data stream comprising a multlplicity of 8 bit data blocks, said method including partitioning the a bit block into two sub-blocks consisting of 5 and 3 contiguous bits, examining each sub-block to determine if any of the individual bits require alteration and altering predetermined bits based on said determination to produce an alternate code pattern, determining the disparity (DO) of the current output sub-block being coded, ascertaining the disparity (D-l) of the last non-zero sub-block coded and selecting a first code pattern as the current output sub-block for certain of the output sub-blocks if the last non-zero disparity in the output code pattern was of a first polarity, assigning the complement of said first code pattern if the last non-zero disparity was of the opposite polarity.

2. A coding method as set forth in Claim 1, wherein the encoding of the 5 bit input data sub-block and the 3 bit input data sub-block is performed substantially concurrently.

3. A coding method as set forth in Claim 2 including automatically adding an extra bit of a predetermined value to each input sub-block to form each output sub-block, said predetermined value being subject to change if it is determined that a predetermined code pattern in said current input sub-block requires changing said extra bit.

4. A coding method as set forth in Claim 3 wherein said alternate code pattern is generated by controlling the complementation of individual bits of said input sub-block and said extra bit in accordance with the logical content thereof to alter same when necessary.

5. A coding method as set forth in Claim 4 wherein the selection of the particular input bits to be complemented is accomplished by logically combining individual predetermined bits of said input data sub-block.

6. A coding method as set forth in Claim 5 wherein the step of computing the disparity of a current sub-block includes the steps of performing a logic analysis of the input bits of said current sub-block and the output of the bit encoding step to determine the disparity of the current sub-block.

7. A coding method as set forth in Claim 6 including the step of notifying the coding system when a specific input 8 bit block is to be representative of a special character outside of the domain of the normal 256 characters representable by the 8 bit code pattern and producing specially encoded output sub-blocks whenever such special character indication accompanies a given 8 bit input sub-block.

8. A coding method as set forth in Claim 7 including factoring said special character indication (K bit) into said bit encoding and disparity determining steps for the 3 bit input sub-block, whereby all of the 4 bit encoded sub-blocks for the special characters have an alternate form which is assigned based solely on a determination of the last non-zero disparity (D-1) sub-block.

9. A coding method as set forth in Claim 8 wherein the step of encoding said special character sub-blocks distinctly from encoded data sub-blocks, includes determining if a predetermined run length and disparity is present in the immediately preceding output sub block and providing a first output sub-block for such special character if said predetermined run length is present and a second output sub-block if said predetermined run length is not present.

10. A coding method as set forth in Claim 9 wherein the step of providing said second output sub-block comprises complementing said first output sub-block in accordance with both a run length and disparity determination.

11. A binary data encoding apparatus for producing a DC balanced (0,4) run length limited rate 8B/10B code from an unconstrained input data stream including means for supplying consecutive 8 bit data blocks to said apparatus, means for partitioning the 8 bit input block into two sub-blocks consisting of 5 and 3 contiguous bits, means for testing each input sub-block to determine if any of the individual bits require alteration during encoding and altering predetermined bits based on said determination to produce an alternate code pattern from said input bit pattern, means for determining the disparity (DO) of the current output sub-block being coded, means for determining the disparity (D-1) of the last non-zero sub-block coded and generating a first code pattern as the current output sub-block for certain of the output sub-blocks if the last non-zero disparity sub-block in the output code stream was of a first polarity, means for generating the complement of said first code pattern if the last non-zero disparity sub-block was of the opposite polarity.

12. A data encoding apparatus as set forth in Claim 11 wherein said means for partitioning includes means for gating the 3 bit and 5 bit input data sub-blocks into the encoding apparatus for substantially concurrent encoding.

13. A data encoding apparatus as set forth in Claim 12 including means for concatenating an extra bit of a predetermined value at the end of each input data sub-block to form each encoded output sub-block, said means for changing the predetermined value of said extra bit if it is found that a predetermined bit pattern is present in said current data input sub-block.

14. A data encoding apparatus as set forth in Claim 13 wherein the means for generating the complement of said first code pattern comprises means for combining the output of said testing means and in said disparity determining means do produce a complementation signal which causes the complement of said first code pattern generated by the system to be gated to the output thereof as the encoded output sub-block.

15. A data encoding apparatus as set forth in Claim 14 wherein said means for complementing includes means for evaluating all of the input data bits of both sub-blocks and also the polarity (negative or positive) of the last non-zero encoded sub-block.

16. A data encoding apparatus as set forth in Claim 15 wherein the means for determining the disparity (DO) of the current sub-block includes means for logically combining the input bits of said current sub-block with the output of the testing means to determine if the disparity of the current sub-block (DO) is zero, positive or negative.

17. A data encoding apparatus as set forth in Claim 16 including means for indicating that a particular 8 bit input block is a special character outside of the domain of the 256 characters normally representable by the 8 bit input data block and means actuable in response to said indication for producing a specially encoded 4 bit output sub-block from said input 8 bit block whenever such special character indication accompanies a given 8 bit input block.

18. A data encoding apparatus as set forth in Claim 17 wherein the means for encoding said special character 3 bit sub-block distinctly from a 3 bit data character input sub-block includes means for determining if a predetermined run length is present in the immediately preceding encoded 6 bit output sub-block for the associated 5 bit data input block and for providing a first 4 bit encoded output sub-block for such special character if said predetermined run length is present and a different 4 bit coded output sub-block if said predetermined run length is not present.

19. A data encoding apparatus as set forth in Claim 18 wherein the means for providing said different 4 bit coded sub-block includes means for complementing said first encoded 4 bit output sub-block.

20. A binary data encoding apparatus for producing a DC balanced (0,4) run length Limited rate 8B/10B code from an unconstrained input data stream including means for supplying consecutive 8 bit data blocks to said apparatus, means for partitioning the 8 bit input block into two sub-blocks consisting of 5 and 3 contiguous bits, said partitioning means including means for gating the 3 bit and 5 bit input data sub-blocks into the encoding apparatus for substantially concurrent encoding in separate circuitry provided for each sub-block, means for concatenating an extra bit of a predetermined value at the end of each input data sub-block to form the additional bit of each encoded output sub-block, means for testing each input sub-block to determine if any of the individual bits or the extra bit require alteration during encoding and altering predetermined bits based on said determination to produce an alternate code pattern from said input bit pattern, means for determining the disparity (DO) of the current output sub-block being coded including means for logically combining the input bits of said current input sub block with the output of 'he testing and altering means to determine if the disparity of the current sub-block (DO) is zero, positive or negative, means for determining the disparity (D-l) of the last non zero sub block coded and generating a first code pattern as the current output sub-block for certain of the input sub-blocks if the last non-zero disparity sub-block in the output code stream was of a first polarity, means for generating the complement of said.
first code pattern if the last non-zero disparity sub-block was of the opposite polarity, said complementing means including means for evaluating all of the input data bits of both sub-blocks and also the polarity (negative or positive) of the last non-zero encoded sub-block.